[S] Change in coreboot[main]: soc/amd/glinda-phoenix: Update pci int defs

[Felix Held (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune.

Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email )

Change subject: soc/amd/glinda-phoenix: Update pci int defs
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Patch Set 2:

(1 comment)

Patchset:

PS2:
> misc1 and misc2 are hpet_l and hpet_h. […]

see register descriptions at the beginning of the FCH registers chapter for those two
IOx00C01_x0A [Intr_Misc1Map] (FCH::IO::IntrMisc1Map)
IOx00C01_x0B [Intr_Misc2Map] (FCH::IO::IntrMisc2Map)

i'd say that having them named with what they do makes things a bit clearer.
to ge the best of both, maybe do this like in the smi.h file:

#define PIRQ_MISC1	0x0a	/* Miscellaneous1 IRQ Settings */
#define PIRQ_HPET_L	PIRQ_MISC1
#define PIRQ_MISC2	0x0b	/* Miscellaneous2 IRQ Settings */
#define PIRQ_HPET_H	PIRQ_MISC2