[M] Change in coreboot[main]: soc/amd/genoa: Hook SMP and SMM init

[Felix Held (Code Review)]

Attention is currently required from: Arthur Heymans, Varshit Pandya.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76523?usp=email )

Change subject: soc/amd/genoa: Hook SMP and SMM init
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Patch Set 5:

(7 comments)

File src/soc/amd/genoa/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/76523/comment/d2c7ac0c_9492ceb6 :
PS5, Line 19: ramstage-y	+= cpu.c
would be good to have this sorted alphabetically

File src/soc/amd/genoa/cpu.c:

https://review.coreboot.org/c/coreboot/+/76523/comment/58316913_fcf943bb :
PS2, Line 42: 	{ X86_VENDOR_AMD, GENOA_A0_CPUID},
            : 	{ X86_VENDOR_AMD, GENOA_A1_CPUID},
            : 	{ X86_VENDOR_AMD, GENOA_B0_CPUID},
> i'd use CPUID_ALL_STEPPINGS_MASK and only have two entries which then will cover all steppings of th […]

Done

File src/soc/amd/genoa/cpu.c:

https://review.coreboot.org/c/coreboot/+/76523/comment/741220ca_02170602 :
PS4, Line 14: /* MP and SMM loading initialization. */
            : void mp_init_cpus(struct bus *cpu_bus)
            : {
            : 	extern const struct mp_ops amd_mp_ops_with_smm;
            : 	if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
            : 		die_with_post_code(POSTCODE_HW_INIT_FAILURE,
            : 				"mp_init_with_smm failed. Halting.\n");
            : 
            : 	/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
            : 	mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
            : 			    FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
            : 
            : 	/* SMMINFO only needs to be set up when booting from S5 */
            : 	if (!acpi_is_wakeup_s3())
            : 		apm_control(APM_CNT_SMMINFO);
            : 
            : }
> this is common code since CB:78013 and can be removed

Done

https://review.coreboot.org/c/coreboot/+/76523/comment/e22ab6b7_8e0ed95b :
PS4, Line 45: 	{ 0, 0 },
> replace with CPU_TABLE_END

Done

File src/soc/amd/genoa/include/soc/cpu.h:

https://review.coreboot.org/c/coreboot/+/76523/comment/0523aa05_a99318bf :
PS5, Line 7: #define GENOA_A1_CPUID      0x00a10f01
not sure if we need to keep this one, since it's now unused

File src/soc/amd/genoa/smihandler.c:

PS4:
> if possible, i'd like this to also be factored out into a patch between the smu patch and the rest o […]

Done

File src/soc/amd/genoa/smihandler.c:

https://review.coreboot.org/c/coreboot/+/76523/comment/1c894654_9d8f4f8f :
PS5, Line 3: /* TODO: Update for Phoenix */
was this verified to still be correct for genoa?