[S] Change in coreboot[main]: soc/intel/pantherlake: Skip exposing CPUJTAG at kernel

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86393?usp=email )

Change subject: soc/intel/pantherlake: Skip exposing CPUJTAG at kernel
......................................................................

soc/intel/pantherlake: Skip exposing CPUJTAG at kernel

This patch prevents exposing the CPU JTAG GPIO pads. These are
internal GPIO pins used for debugging the SoC and should not be
configurable from the kernel pinctrl driver.

TEST=Able to build and boot google/fatat. Decompile ACPI table
using iasl and ensure CPUJTAG entry not present.

Change-Id: I4d920acb95275fbf72b83b822eddc41829511626
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86393
Tested-by: build bot (Jenkins) 
Reviewed-by: Dinesh Gehlot 
Reviewed-by: Jayvik Desai 
Reviewed-by: Eric Lai 
---
M src/soc/intel/pantherlake/acpi/gpio.asl
M src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
2 files changed, 8 insertions(+), 36 deletions(-)

Approvals:
  Dinesh Gehlot: Looks good to me, approved
  Jayvik Desai: Looks good to me, approved
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved

diff --git a/src/soc/intel/pantherlake/acpi/gpio.asl b/src/soc/intel/pantherlake/acpi/gpio.asl
index c16513b..653f00b 100644
--- a/src/soc/intel/pantherlake/acpi/gpio.asl
+++ b/src/soc/intel/pantherlake/acpi/gpio.asl
@@ -27,10 +27,10 @@
    	Local1 = Arg0 - COM1_GRP_PAD_START
    }
    /* GPIO Community 3 */
-	If (Arg0 >= COM3_GRP_PAD_START && Arg0 <= COM3_GRP_PAD_END)
+	If (Arg0 >= GPP_H00 && Arg0 <= COM3_GRP_PAD_END)
    {
    	Local0 = PID_GPIOCOM3
-		Local1 = Arg0 - COM3_GRP_PAD_START
+		Local1 = Arg0 - GPP_H00
    }
    /* GPIO Community 4 */
    If (Arg0 >= COM4_GRP_PAD_START && Arg0 <= COM4_GRP_PAD_END)
@@ -438,7 +438,7 @@
    }
 }

-/* GPIO Community 3: CPUJTAG, GPP_H, GPP_A, VGPIO3 */
+/* GPIO Community 3: GPP_H, GPP_A, VGPIO3 */
 Device (GPI3)
 {
    Name (_HID, ACPI_GPIO_HID)
@@ -471,7 +471,7 @@
    		Package (0x02)
    		{
    			"intc-gpio-group-count",
-				NUM_COM3_GROUPS
+				NUM_COM3_GROUPS - 1 /* Skip CPUJTAG */
    		},

Package (0x02)
@@ -510,12 +510,6 @@
    	{
    		Package (0x02)
    		{
-				"intc-gpio-group-0-subproperties",
-				JTAG
-			},
-
-			Package (0x02)
-			{
    			"intc-gpio-group-1-subproperties",
    			GPPH
    		},
@@ -533,31 +527,10 @@
    		}
    	}
    })
-	/* first bank/group in community 3: CPUJTAG */
-	Name (JTAG, Package (0x02)
-	{
-		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-		Package (0x03)
-		{
-			Package (0x02)
-			{
-				"intc-gpio-group-name",
-				GPP_CPUJTAG_NAME
-			},
-
-			Package (0x02)
-			{
-				"intc-gpio-pad-count",
-				NUM_GRP_CPUJTAG_PADS
-			},
-
-			Package (0x02)
-			{
-				"intc-gpio-group-offset",
-				GPP_CPUJTAG_START_OFFSET
-			}
-		}
-	})
+	/*
+	 * Don't expose first bank/group in community 3: CPUJTAG because
+	 * CPUJTAG doesn't required to be controlled by kernel pinctrl driver.
+	 */
    /* 2nd bank/group in community 3: GPP_H */
    Name (GPPH, Package (0x02)
    {
diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
index 0937d1e..69f2f7e 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
@@ -37,7 +37,6 @@
 #define GPP_C_NAME		"GPP_C"
 #define GPP_F_NAME		"GPP_F"
 #define GPP_E_NAME		"GPP_E"
-#define GPP_CPUJTAG_NAME	"GPUJTAG"
 #define GPP_H_NAME		"GPP_H"
 #define GPP_A_NAME		"GPP_A"
 #define GPP_VGPIO3_NAME		"vGPIO_3"