[S] Change in coreboot[main]: soc/intel/alderlake: Do lazy reset after disabling UFS

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84935?usp=email )

(

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/alderlake: Do lazy reset after disabling UFS
......................................................................

soc/intel/alderlake: Do lazy reset after disabling UFS

If the mainboard expects upcoming reset, then skip the reset after
disabling UFS. This will reduce the number of resets during firmware
update.

BUG=b:375444631
TEST=Build Brox BIOS image and boot to OS. Perform a firmware update and
confirm that the number of reset is reduced by 2 resets.

Change-Id: I4399555302ec23a76f89f406f437f311eea0ef99
Signed-off-by: Karthikeyan Ramasubramanian 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84935
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Menzel 
---
M src/soc/intel/alderlake/include/soc/romstage.h
M src/soc/intel/alderlake/romstage/romstage.c
2 files changed, 17 insertions(+), 1 deletion(-)

Approvals:
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h
index 679d538..574c9b7 100644
--- a/src/soc/intel/alderlake/include/soc/romstage.h
+++ b/src/soc/intel/alderlake/include/soc/romstage.h
@@ -20,4 +20,15 @@
    BOARD_TYPE_SERVER  = 8
 };

+/*
+ * Default implementation indicates that the mainboard does not expect another reset.
+ * Mainboards can override the default implementation to indicate whether they expect
+ * another reset eg. FW Sync for another component on the mainboard. Some silicon init
+ * code eg. disabling UFS, can use this hint to suppress any redundant resets that they
+ * trigger. If the mainboard does not expect another reset, then the silicon init code
+ * can trigger their required reset.
+ *
+ * Return: true when the mainboard expects another reset, false otherwise.
+ */
+bool mainboard_expects_another_reset(void);
 #endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index ff600db..2f50cd2 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -32,6 +32,11 @@
 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
 #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS  (1 << 8)

+bool __weak mainboard_expects_another_reset(void)
+{
+	return false;
+}
+
 static void disable_ufs(void)
 {
    /* disable USF0 */
@@ -185,7 +190,7 @@
    		 (CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) {
    	printk(BIOS_INFO, "Disabling UFS controllers\n");
    	disable_ufs();
-		if (ps->prev_sleep_state == ACPI_S5) {
+		if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) {
    		printk(BIOS_INFO, "Warm Reset after disabling UFS controllers\n");
    		system_reset();
    	}