[XS] Change in coreboot[main]: soc/intel/meteorlake: Add doc reference for thunderbolt port number

[Jérémy Compostella (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun.

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85820?usp=email )

Change subject: soc/intel/meteorlake: Add doc reference for thunderbolt port number
......................................................................

soc/intel/meteorlake: Add doc reference for thunderbolt port number

Document #640228 Meteor Lake - U/H and U Type4 Processor - 2.3 Device
IDs - Table 8 "Other Device ID" IDs - Table 8 "Other Device ID"
specifies that the first Thunderbolt PCIe root port number is 16.

Change-Id: Ic394aa6795105ff613f30e8aa0ffa45500c6332a
Signed-off-by: Jeremy Compostella 
---
M src/soc/intel/meteorlake/pcie_rp.c
1 file changed, 5 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/85820/1

diff --git a/src/soc/intel/meteorlake/pcie_rp.c b/src/soc/intel/meteorlake/pcie_rp.c
index 7cfe3ed..7c47e3e 100644
--- a/src/soc/intel/meteorlake/pcie_rp.c
+++ b/src/soc/intel/meteorlake/pcie_rp.c
@@ -6,9 +6,11 @@
 #include <soc/soc_info.h>

/*
- * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe
- * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's
- * PCIe remapping logic can return correct index (0-based)
+ * Document #640228 Meteor Lake - U/H and U Type4 Processor - 2.3 Device IDs - Table 8 "Other
+ * Device ID" specifies that the first Thunderbolt PCIe root port number is 16. TBT's LCAP
+ * registers return port index which starts from 16 (usually for other PCIe root ports index
+ * starts from 1). Thus, keeping lcap_port_base 16 for TBT, so that coreboot's PCIe remapping
+ * logic can return a correct index (0-based).
  */

static const struct pcie_rp_group tbt_rp_groups[] = {