Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35617 )
Change subject: soc/intel/fsp_broadwell_de: Enable SSE and SSE2 ......................................................................
soc/intel/fsp_broadwell_de: Enable SSE and SSE2
Apparently romcc-bootblock just barely built without XMM registers.
Change-Id: Ie7b1101f47c2dfb718bef99f8c05f9d575c821cd Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/fsp_broadwell_de/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35617/1
diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 9c91d7c..88ad586 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -18,6 +18,7 @@ select PARALLEL_MP select SMP select IOAPIC + select SSE2 select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35617 )
Change subject: soc/intel/fsp_broadwell_de: Enable SSE and SSE2 ......................................................................
Patch Set 1: Code-Review+1
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35617 )
Change subject: soc/intel/fsp_broadwell_de: Enable SSE and SSE2 ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35617 )
Change subject: soc/intel/fsp_broadwell_de: Enable SSE and SSE2 ......................................................................
Patch Set 1:
Please test with hardware you have. Patrick reported some failing fsp-broadwell-de builds (no details available) with SSE2 enabled. It was not clear to me if he means 'CONFIG_SSE2=y' or 'gcc -msse2'.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35617 )
Change subject: soc/intel/fsp_broadwell_de: Enable SSE and SSE2 ......................................................................
soc/intel/fsp_broadwell_de: Enable SSE and SSE2
Apparently romcc-bootblock just barely built without XMM registers.
Change-Id: Ie7b1101f47c2dfb718bef99f8c05f9d575c821cd Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35617 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/soc/intel/fsp_broadwell_de/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Werner Zeh: Looks good to me, approved
diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 94eff07..6c74a74 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -18,6 +18,7 @@ select PARALLEL_MP select SMP select IOAPIC + select SSE2 select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE
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Kyösti Mälkki (Code Review) -
Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Werner Zeh (Code Review)