[S] Change in coreboot[main]: soc/amd/mendocino: Add DBG2 table

[Bao Zheng (Code Review)]

Attention is currently required from: Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Raul Rangel, Tim Wawrzynczak, Zheng Bao.

Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79174?usp=email )

Change subject: soc/amd/mendocino: Add DBG2 table
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Patch Set 3:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/79174/comment/38446473_058f0105 :
PS2, Line 9: 240426142
> 303689867

Done

File src/soc/amd/mendocino/agesa_acpi.c:

https://review.coreboot.org/c/coreboot/+/79174/comment/d7b71bfd_772b9ac6 :
PS2, Line 30: Add table
> DBG2?

Done

https://review.coreboot.org/c/coreboot/+/79174/comment/780ba198_85bddfaf :
PS2, Line 31: 0xfedc9000
> I would probably use the configured console: […]

Done.
There is not field for baudrate in DBG2.

https://review.coreboot.org/c/coreboot/+/79174/comment/7e156622_a6924470 :
PS2, Line 31: 	current = acpi_16550_write_dbg2_uart(rsdp, current, 0xfedc9000, NULL);
> shouldn't this call be put into an if CONFIG(AMD_SOC_CONSOLE_UART) block? i agree with Raul that the […]

Done