Change in coreboot[master]: arch/x86: Implement cache_payload_destination

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64429 )

Change subject: arch/x86: Implement cache_payload_destination
......................................................................

arch/x86: Implement cache_payload_destination

LZMA requires the target mem address to be cacheable otherwise
the whole decompression will be lenthy.
There are corner cases could happen that the destination
mem of payload is set to uncacheable.
On ADL, we see mem 0x30000000 is set to uncacheable and causes
~18s delay.

BUG=b:225766934

Change-Id: I5c74788c1fb95d6ed5c699c1e6e3e27d9486896e
Signed-off-by: Kane Chen 
---
M src/arch/x86/boot.c
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/64429/1

diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c
index c50ec0e..3c77292 100644
--- a/src/arch/x86/boot.c
+++ b/src/arch/x86/boot.c
@@ -8,6 +8,8 @@
 #include <ip_checksum.h>
 #include <symbols.h>
 #include <assert.h>
+#include <cpu/x86/mtrr.h>
+#include <lib.h>

int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size)
 {
@@ -20,6 +22,18 @@
    return 0;
 }

+void cache_payload_destination(void *dest, size_t memsz)
+{
+	/* Round to power of two */
+	size_t payload_size_alignment = 1UL << (log2_ceil(memsz));
+	const int type = MTRR_TYPE_WRBACK;
+	int mtrr = get_free_var_mtrr();
+	if (mtrr != -1) {
+		printk(BIOS_DEBUG, "Set mem 0x%p, size 0x%lx as WB\n", dest, memsz);
+		set_var_mtrr(mtrr, (unsigned int)dest, payload_size_alignment, type);
+	}
+}
+
 void arch_prog_run(struct prog *prog)
 {
 #if ENV_RAMSTAGE && ENV_X86_64