[S] Change in coreboot[main]: arch/riscv: add Kconfig variable RISCV_HAS_MENVCFG

[ron minnich (Code Review)]

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81410?usp=email )

Change subject: arch/riscv: add Kconfig variable RISCV_HAS_MENVCFG
......................................................................

arch/riscv: add Kconfig variable RISCV_HAS_MENVCFG

Older parts do not have the menvcfg csr.
Provide a Kconfig variable, default y, to enable it.
Check the variable in the payload code, when coreboot SBI
is used, and print out if it is enabled.

Add constants for this new CSR.

Signed-off-by: Ronald G Minnich

Change-Id: I627dde377708cde2491d4abe625c482d64f7aa87
---
M src/arch/riscv/Kconfig
M src/arch/riscv/include/arch/encoding.h
M src/arch/riscv/payload.c
3 files changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81410/1

diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 971dda3..e564480 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -110,4 +110,12 @@
 config RISCV_WORKING_HARTID
    int

+# Newer SoC have the menvconfig register.
+# Older SoC, such as the SiFive FU[57]40, that
+# do not have this register, should set this
+# to n.
+config RISCV_HAS_MENVCONFIG
+	bool
+	default y
+
 endif # if ARCH_RISCV
diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h
index 4f01e5c..6ab38bb 100644
--- a/src/arch/riscv/include/arch/encoding.h
+++ b/src/arch/riscv/include/arch/encoding.h
@@ -800,6 +800,8 @@
 #define CSR_MIE 0x304
 #define CSR_MTVEC 0x305
 #define CSR_MCOUNTEREN 0x306
+#define CSR_MENVCFG 0x30a
+#define CSR_MENVCFGH 0x31a
 #define CSR_MSCRATCH 0x340
 #define CSR_MEPC 0x341
 #define CSR_MCAUSE 0x342
@@ -1292,6 +1294,8 @@
 DECLARE_CSR(mie, CSR_MIE)
 DECLARE_CSR(mtvec, CSR_MTVEC)
 DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(menvcfg, CSR_MENVCFG)
+DECLARE_CSR(menvcfgh, CSR_MENVCFGH)
 DECLARE_CSR(mscratch, CSR_MSCRATCH)
 DECLARE_CSR(mepc, CSR_MEPC)
 DECLARE_CSR(mcause, CSR_MCAUSE)
diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
index 7c6e0f4..8a5ae80 100644
--- a/src/arch/riscv/payload.c
+++ b/src/arch/riscv/payload.c
@@ -68,6 +68,9 @@
    	 */
    	close_pmp();

+		if (CONFIG(RISCV_HAS_MENVCONFIG)) {
+			printk(BIOS_DEBUG, "This part has menvconfig\n");
+		}
    	status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S);
    	/* Trap vector base address point to the payload */
    	write_csr(stvec, doit);