[M] Change in coreboot[main]: mb/google/nissa/var/rull: Match VBT with SSFC

[Rui Zhou (Code Review)]

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85875?usp=email )

Change subject: mb/google/nissa/var/rull: Match VBT with SSFC
......................................................................

mb/google/nissa/var/rull: Match VBT with SSFC

We want to configure different VBT timings for panels of different sizes
and distinguish them through SSFC. We select the reserved bit 6 of SSFC
as the flag bit. When using a AUO panel, set this bit to 1.
Without splitting, the platform_BootPerf test will fail.

BUG=b:379835056
TEST=can match VBT with SSFC
-When SSFC is set to 0x40:
$ cat /sys/firmware/log | grep vbt
Bit 6 of SSFC is 1, use vbt-teliks-auo.bin

Change-Id: I413179af0a1346b7d21f17d728d6846c30707978
Signed-off-by: Rui Zhou 
---
M src/mainboard/google/brya/variants/rull/variant.c
1 file changed, 58 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/85875/1

diff --git a/src/mainboard/google/brya/variants/rull/variant.c b/src/mainboard/google/brya/variants/rull/variant.c
index 4f8fd47..d98db5f 100644
--- a/src/mainboard/google/brya/variants/rull/variant.c
+++ b/src/mainboard/google/brya/variants/rull/variant.c
@@ -2,6 +2,9 @@

#include <baseboard/variants.h>
 #include <chip.h>
+#include <console/console.h>
+#include <drivers/intel/gma/opregion.h>
+#include <ec/google/chromeec/ec.h>
 #include <fw_config.h>
 #include <sar.h>
 #include <soc/gpio_soc_defs.h>
@@ -41,3 +44,58 @@
    graphics_gtt_rmw(TRANS_DDI_FUNC_CTL2_A, ~TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS,
    	TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS);
 }
+
+static int get_ssfc(uint32_t *val)
+{
+	static uint32_t known_value;
+	static enum {
+		SSFC_NOT_READ,
+		SSFC_AVAILABLE,
+	} ssfc_state = SSFC_NOT_READ;
+
+	if (ssfc_state == SSFC_AVAILABLE) {
+		*val = known_value;
+		return 0;
+	}
+
+	/*
+	 * If SSFC field is not in the CBI then the value of SSFC will be 0 for
+	 * further processing later since 0 of each bits group means default
+	 * component in a variant. For more detail, please refer to cbi_ssfc.h.
+	 */
+	if (google_chromeec_cbi_get_ssfc(&known_value) != 0) {
+		printk(BIOS_DEBUG, "SSFC not set in CBI\n");
+		return -1;
+	}
+
+	ssfc_state = SSFC_AVAILABLE;
+	*val = known_value;
+	printk(BIOS_INFO, "SSFC 0x%x.\n", known_value);
+	return 0;
+}
+
+const char *mainboard_vbt_filename(void)
+{
+	uint32_t ssfc;
+	if (get_ssfc(&ssfc)) {
+		printk(BIOS_INFO, "Failed to read SSFC, using default vbt-rull.bin\n");
+		return "vbt-rull.bin";
+	}
+
+	/*
+	 * Determine if the panel is auo based on the SSFC register.
+	 *
+	 * Bit 6 of the SSFC register indicates the panel vendor:
+	 *   0: other pannel
+	 *   1: auo panel
+	 */
+	bool is_panel_auo = (ssfc >> 6) & 0x1;
+
+	if (is_panel_auo) {
+		printk(BIOS_INFO, "Bit 6 of SSFC is 1, use vbt-rull-auo.bin\n");
+		return "vbt-rull-auo.bin";
+	}
+
+	printk(BIOS_INFO, "Bit 6 of SSFC is 0, use vbt-rull.bin\n");
+	return "vbt-rull.bin";
+}