Sheng Lean Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60899 )
Change subject: mb/prodrive/atlas: Add new mainboard based on adlrvp ......................................................................
mb/prodrive/atlas: Add new mainboard based on adlrvp
This is a initial mainboard code cloned from adlrvp aimed to serve as base for further mainboard check-ins. This commit simply copies the mainboard directory and adjusts the naming to match the new board's name. Besides, This commit also remove ADL-M, ADL-N, ADL-P LPDDR & ADL-P DDR4 RVP boards related code as Atlas is using ADL-P DDR5 boards as main reference. Follow-up commits will introduce the needed changes for the new mainboard.
Signed-off-by: Lean Sheng Tan sheng.tan@9elements.com Change-Id: Ia3129f68c73969604edcd290c3e50ad219cf88d9 --- A src/mainboard/prodrive/atlas/Kconfig A src/mainboard/prodrive/atlas/Kconfig.name A src/mainboard/prodrive/atlas/Makefile.inc A src/mainboard/prodrive/atlas/board_id.c A src/mainboard/prodrive/atlas/board_id.h A src/mainboard/prodrive/atlas/board_info.txt A src/mainboard/prodrive/atlas/bootblock.c A src/mainboard/prodrive/atlas/chromeos.fmd A src/mainboard/prodrive/atlas/devicetree.cb A src/mainboard/prodrive/atlas/dsdt.asl A src/mainboard/prodrive/atlas/early_gpio.c A src/mainboard/prodrive/atlas/gpio.c A src/mainboard/prodrive/atlas/gpio.h A src/mainboard/prodrive/atlas/mainboard.c A src/mainboard/prodrive/atlas/memory.c A src/mainboard/prodrive/atlas/ramstage.c A src/mainboard/prodrive/atlas/romstage_fsp_params.c A src/mainboard/prodrive/atlas/spd/Makefile.inc A src/mainboard/prodrive/atlas/spd/adlrvp_ddr5_mr.spd.hex A src/mainboard/prodrive/atlas/spd/empty.spd.hex A src/mainboard/prodrive/atlas/variants.h 21 files changed, 1,517 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/60899/1
diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig new file mode 100644 index 0000000..15b3aa4 --- /dev/null +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -0,0 +1,66 @@ +config BOARD_PRODRIVE_ATLAS_BASEBOARD + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_I2C_MAX98373 + select DRIVERS_INTEL_DPTF + select DRIVERS_INTEL_MIPI_CAMERA + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_SOUNDWIRE_ALC711 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + select SOC_INTEL_ALDERLAKE_PCH_P + select GEN3_EXTERNAL_CLOCK_BUFFER + +if BOARD_PRODRIVE_ATLAS_BASEBOARD + +config MAINBOARD_FAMILY + string + default "PRODRIVE_ATLAS_SERIES" + +config MAINBOARD_PART_NUMBER + default "Atlas ADL-P" + +config MAINBOARD_DIR + default "prodrive/atlas" + +config MAINBOARD_VENDOR + string + default "Prodrive" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "Prodrive Techonologies B.V." + +config DIMM_SPD_SIZE + default 512 + +config UART_FOR_CONSOLE + int + default 0 + +config GEN3_EXTERNAL_CLOCK_BUFFER + bool + default n + help + Support external Gen-3 clock chip for ADL-P. + `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` provides feed clock to discrete buffer + for further distribution to platform. SRCCLKREQB[7:9] maps to internal + SRCCLKREQB[6]. If any of them asserted, SRC buffer + `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` gets enabled. + +config CLKSRC_FOR_EXTERNAL_BUFFER + depends on GEN3_EXTERNAL_CLOCK_BUFFER + int + default 6 # CLKSRC 6 +endif #BOARD_PRODRIVE_ATLAS_BASEBOARD diff --git a/src/mainboard/prodrive/atlas/Kconfig.name b/src/mainboard/prodrive/atlas/Kconfig.name new file mode 100644 index 0000000..f4304a0 --- /dev/null +++ b/src/mainboard/prodrive/atlas/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_PRODRIVE_ATLAS + bool "Atlas" + select BOARD_PRODRIVE_ATLAS_BASEBOARD diff --git a/src/mainboard/prodrive/atlas/Makefile.inc b/src/mainboard/prodrive/atlas/Makefile.inc new file mode 100644 index 0000000..0d8c6da --- /dev/null +++ b/src/mainboard/prodrive/atlas/Makefile.inc @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd + +bootblock-y += bootblock.c +bootblock-y += early_gpio.c +ramstage-y += gpio.c + +romstage-y += romstage_fsp_params.c +romstage-y += board_id.c +romstage-y += memory.c + +ramstage-y += mainboard.c +ramstage-y += board_id.c +ramstage-y += ramstage.c diff --git a/src/mainboard/prodrive/atlas/board_id.c b/src/mainboard/prodrive/atlas/board_id.c new file mode 100644 index 0000000..ebd3921 --- /dev/null +++ b/src/mainboard/prodrive/atlas/board_id.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <ec/acpi/ec.h> +#include <types.h> + +#include "board_id.h" + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + MAYBE_STATIC_NONZERO int id = -1; + + if (id < 0) { + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + id = recv_ec_data() << 8; + id |= recv_ec_data(); + } + } + return (id & BOARD_ID_MASK); +} diff --git a/src/mainboard/prodrive/atlas/board_id.h b/src/mainboard/prodrive/atlas/board_id.h new file mode 100644 index 0000000..2988127 --- /dev/null +++ b/src/mainboard/prodrive/atlas/board_id.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ +#define _MAINBOARD_COMMON_BOARD_ID_H_ + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0d +/* Bit 5:0 for Board ID */ +#define BOARD_ID_MASK 0x3f + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/prodrive/atlas/board_info.txt b/src/mainboard/prodrive/atlas/board_info.txt new file mode 100644 index 0000000..937a521 --- /dev/null +++ b/src/mainboard/prodrive/atlas/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Prodrive +Board name: Atlas +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/prodrive/atlas/bootblock.c b/src/mainboard/prodrive/atlas/bootblock.c new file mode 100644 index 0000000..da185e3 --- /dev/null +++ b/src/mainboard/prodrive/atlas/bootblock.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmio.h> +#include <bootblock_common.h> +#include <cf9_reset.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <cpu/intel/cpu_ids.h> +#include <fmap.h> +#include <intelblocks/pmclib.h> + +#include "variants.h" + +#define SI_DESC_REGION "SI_DESC" +#define SI_DESC_REGION_SZ 4096 +#define PMC_DESC_7_BYTE3 0xc32 + +/* Flash Master 1 : HOST/BIOS */ +#define FLMSTR1 0x80 + +/* Flash signature Offset */ +#define FLASH_SIGN_OFFSET 0x10 +#define FLMSTR_WR_SHIFT_V2 20 +#define FLASH_VAL_SIGN 0xFF0A55A + +/* It checks whether host(Flash Master 1) has write access to the Descriptor Region or not */ +static int is_descriptor_writeable(uint8_t *desc) +{ + /* Check flash has valid signature */ + if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { + printk(BIOS_DEBUG, "Flash Descriptor is not valid\n"); + return 0; + } + + /* Check host has write access to the Descriptor Region */ + if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + printk(BIOS_DEBUG, "Host doesn't have write access to Descriptor Region\n"); + return 0; + } + + return 1; +} + +/* It updates PMC Descriptor in the Descriptor Region */ +static void configure_pmc_descriptor(void) +{ + uint8_t si_desc_buf[SI_DESC_REGION_SZ]; + struct region_device desc_rdev; + + if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); + return; + } + + if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + return; + } + + if (!is_descriptor_writeable(si_desc_buf)) + return; + + if (si_desc_buf[PMC_DESC_7_BYTE3] != 0x40) { + printk(BIOS_DEBUG, "Update of PMC Descriptor is not required!\n"); + return; + } + + si_desc_buf[PMC_DESC_7_BYTE3] = 0x44; + + if (rdev_eraseat(&desc_rdev, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); + return; + } + + if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) + != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to update Descriptor Region\n"); + return; + } + + printk(BIOS_DEBUG, "Update of PMC Descriptor successful, trigger GLOBAL RESET\n"); + + pmc_global_reset_enable(true); + do_full_reset(); + die("Failed to trigger GLOBAL RESET\n"); +} + +void bootblock_mainboard_early_init(void) +{ + variant_configure_early_gpio_pads(); +} +void bootblock_mainboard_init(void) +{ + if (cpu_get_cpuid() == CPUID_ALDERLAKE_A0) + configure_pmc_descriptor(); +} diff --git a/src/mainboard/prodrive/atlas/chromeos.fmd b/src/mainboard/prodrive/atlas/chromeos.fmd new file mode 100644 index 0000000..53469de --- /dev/null +++ b/src/mainboard/prodrive/atlas/chromeos.fmd @@ -0,0 +1,56 @@ +FLASH 32M { + SI_ALL 6M { + SI_DESC 4K + SI_EC 512K + SI_ME { + CSE_LAYOUT 8K + CSE_RO 1588K + CSE_DATA 512K + # 64-KiB aligned to optimize RW erases during CSE update. + CSE_RW 3520K + } + } + SI_BIOS 26M { + RW_SECTION_A 8M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 3520K + } + RW_LEGACY(CBFS) 1M + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 192K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 128K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # This section starts at the 16M boundary in SPI flash. + # ADL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 3520K + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb new file mode 100644 index 0000000..2c45e85 --- /dev/null +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -0,0 +1,446 @@ +chip soc/intel/alderlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # Enable HECI1 interface + register "HeciEnabled" = "1" + + # FSP configuration + + # Enable CNVi BT + register "CnviBtCore" = "true" + + # Sagv Configuration + register "SaGv" = "SaGv_Enabled" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Enable PCH PCIE RP 5 using CLK 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 6 using CLK 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 8 using free running CLK (0x80) + # Clock source is shared with LAN and hence marked as free running. + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING" + + # Enable PCH PCIE RP 9 using CLK 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 11 for optane + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + + # Hybrid storage mode + register "HybridStorageMode" = "1" + + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + }" + + # Enable CPU PCIE RP 2 using CLK 3 + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_req = 3, + .clk_src = 3, + }" + + # Enable CPU PCIE RP 3 using CLK 4 + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .clk_req = 4, + .clk_src = 4, + }" + + register "SataSalpSupport" = "1" + + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + # Enable EDP in PortA + register "DdiPortAConfig" = "1" + # Enable HDMI in Port B + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + # TCSS USB3 + register "TcssAuxOri" = "0" + + register "s0ix_enable" = "1" + register "dptf_enable" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" + register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" + register "PchHdaIDispCodecEnable" = "1" + + register "CnviBtAudioOffload" = "true" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref pcie5 on end + device ref igpu on end + device ref dtt on + chip drivers/intel/dptf + + ## sensor information + register "options.tsr[0].desc" = ""Ambient"" + register "options.tsr[1].desc" = ""Battery"" + register "options.tsr[2].desc" = ""DDR"" + register "options.tsr[3].desc" = ""Skin"" + + ## Active Policy + # TODO: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(95, 90), + TEMP_PCT(90, 80), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(80, 90), + TEMP_PCT(70, 80), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 35000, + .max_power = 45000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 56000, + .max_power = 56000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1"" + register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0"" + register "cio2_prt[0]" = "2" + register "cio2_prt[1]" = "1" + device generic 0 on end + end + end + device ref pcie4_0 on end + device ref pcie4_1 on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref crashlog off end + device ref tcss_xhci on end + device ref tcss_dma0 on end + device ref tcss_dma1 on end + device ref xhci on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on end + device ref i2c1 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\_SB.PCI0.I2C1.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref sata on end + device ref i2c5 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + end + device ref pcie_rp1 on end + device ref pcie_rp3 on end # W/A to FSP issue + device ref pcie_rp4 on end # W/A to FSP issue + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp11 on end + device ref uart0 on end + device ref gspi0 on end + device ref p2sb on end + device ref hda on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + end + end + end + device ref smbus on end + end +end diff --git a/src/mainboard/prodrive/atlas/dsdt.asl b/src/mainboard/prodrive/atlas/dsdt.asl new file mode 100644 index 0000000..3b9af12 --- /dev/null +++ b/src/mainboard/prodrive/atlas/dsdt.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +#include "gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/prodrive/atlas/early_gpio.c b/src/mainboard/prodrive/atlas/early_gpio.c new file mode 100644 index 0000000..3e5a400 --- /dev/null +++ b/src/mainboard/prodrive/atlas/early_gpio.c @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> + +#include "gpio.h" +#include "variants.h" + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), + /* SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + + /* CPU PCIe VGPIO for RP0 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, PLTRST, NF1), + + /* CPU PCIe vGPIO for RP1 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, PLTRST, NF1), + + /* CPU PCIe vGPIO for RP2 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1), + + /* CPU PCIe vGPIO for RP3 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config early_uart_gpio_table[] = { + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +void variant_configure_early_gpio_pads(void) +{ + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); + + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/prodrive/atlas/gpio.c b/src/mainboard/prodrive/atlas/gpio.c new file mode 100644 index 0000000..9ae38d4 --- /dev/null +++ b/src/mainboard/prodrive/atlas/gpio.c @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> + +#include "gpio.h" +#include "variants.h" + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* SSD1_PWREN CPU SSD1 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* SSD1_RESET CPU SSD1 */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* WLAN RST# */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* WIFI_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT), + /* x4 PCIE slot1 PWREN */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + /* x4 PCIE slot 1 RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* Retimer Force Power */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + /* PEG Slot RST# */ + PAD_CFG_GPO(GPP_B2, 1, PLTRST), + /* M.2 SSD_2 Reset */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* Audio Codec INT N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* THC1 SPI2 RST# */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), + /* EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* WIFI RF KILL */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + /* DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + /* WWAN WAKE N*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), + /* WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 1, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), + /* WWAN_PERST# */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* PEG_SLOT_WAKE_N */ + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), + /* CAM CONN1 CLKEN */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + /* CPU SSD2 PWREN */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* CPU SSD2 RST# */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* Sata direct Power */ + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + /* M.2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* SRCCLK_OEB7 */ + PAD_CFG_GPO(GPP_A7, 0, PLTRST), + /* SRCCLK_OEB6 */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), + + /* CAM1_RST */ + PAD_CFG_GPO(GPP_R5, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), + /* M.2_SSD_PDET_R */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* THC0 SPI1 CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), + /* THC0 SPI1 IO 1 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2), + /* THC0 SPI1 IO 2 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), + /* THC0 SPI IO 3 */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), + /* THC1 SPI1 RSTB */ + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2), + /* UART_RX(1) */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* UART_RX(2) */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* UART_RX(4) */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), + /* UART_RX(5) */ + PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1), + /* UART_RX(6) */ + PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1), + + /* UART_TX(1) */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* UART_TX(2) */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* UART_TX(4) */ + PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1), + /* UART_TX(5) */ + PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1), + /* UART_TX(6) */ + PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1), + + /* UART_RTS(1) */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* UART_RTS(2) */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* UART_RTS(4) */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), + /* UART_RTS(5) */ + PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1), + /* UART_RTS(6) */ + PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1), + + /* UART_CTS(1) */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + /* UART_CTS(2) */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + /* UART_CTS(4) */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), + /* UART_CTS(5) */ + PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1), + /* UART_CTS(6) */ + PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1), + + /* SPI_MOSI(1) */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* SPI_MOSI(2) */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + + /* SPI_MIS0(1) */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* SPI_MIS0(2) */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + + /* SPI_CLK(1) */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* SPI_CLK(2) */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + + /* SPI_CS(0, 1) */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* SPI_CS(1, 0) */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* SPI_CS(2, 0) */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* I2C_SCL(5) */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* I2C_SDA(5) */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + + /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* I2S0_TXD */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* I2S0_RXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + + /* I2S2_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* I2S2_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* I2S2_TXD */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* I2S2_RXD */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* I2S_MCLK2_INOUT */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + + /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* SNDW1_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* SNDW2_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* SNDW2_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* SNDW3_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* SNDW4_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* SNDW4_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* SATA DEVSLP */ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), + + /* SATA LED pin */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* USB2 OC0 pins */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* USB2 OC3 pins */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPIO pin for PCIE SRCCLKREQB */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_NC(GPP_D8, NONE), + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + + /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + + /* HPD_1 (E14) and HPD_2 (A18) pins */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + PAD_NC(GPP_H23, NONE), + + /* A21 : HDMI CRLS CTRLCLK */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + /* A22 : HDMI CRLS CTRLDATA */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/prodrive/atlas/gpio.h b/src/mainboard/prodrive/atlas/gpio.h new file mode 100644 index 0000000..9a1c585 --- /dev/null +++ b/src/mainboard/prodrive/atlas/gpio.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#define GPIO_EC_IN_RW GPP_E7 + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/prodrive/atlas/mainboard.c b/src/mainboard/prodrive/atlas/mainboard.c new file mode 100644 index 0000000..d147c50 --- /dev/null +++ b/src/mainboard/prodrive/atlas/mainboard.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/opregion.h> +#include <soc/gpio.h> +#include <smbios.h> +#include <stdint.h> +#include <string.h> +#include <fw_config.h> + +#include "board_id.h" +#include "gpio.h" +#include "variants.h" + +const char *smbios_system_sku(void) +{ + static char sku_str[7] = ""; + uint8_t sku_id = get_board_id(); + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + return sku_str; +} + +static void mainboard_init(void *chip_info) +{ + variant_configure_gpio_pads(); + + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; + +const char *mainboard_vbt_filename(void) +{ + uint8_t sku_id = get_board_id(); + switch (sku_id) { + case ADL_P_DDR5_1: + case ADL_P_DDR5_2: + return "vbt_adlrvp_ddr5.bin"; + default: + return "vbt.bin"; + } +} diff --git a/src/mainboard/prodrive/atlas/memory.c b/src/mainboard/prodrive/atlas/memory.c new file mode 100644 index 0000000..f0e3dbb --- /dev/null +++ b/src/mainboard/prodrive/atlas/memory.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/romstage.h> +#include "board_id.h" +#include "variants.h" + +static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistor */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = { 50, 30, 30, 30, 27 }, + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + + .ddr_config = { + .dq_pins_interleaved = false, + } +}; + +const struct mb_cfg *variant_memory_params(void) +{ + int board_id = get_board_id(); + + switch (board_id) { + case ADL_P_DDR5_1: + case ADL_P_DDR5_2: + return &ddr5_mem_config; + default: + die("unsupported board id : 0x%x\n", board_id); + } +} diff --git a/src/mainboard/prodrive/atlas/ramstage.c b/src/mainboard/prodrive/atlas/ramstage.c new file mode 100644 index 0000000..19de990 --- /dev/null +++ b/src/mainboard/prodrive/atlas/ramstage.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <soc/gpio_soc_defs.h> +#include <soc/pci_devs.h> +#include <soc/soc_chip.h> +#include <string.h> +#include <drivers/intel/dptf/chip.h> +#include <intelblocks/power_limit.h> + +#include "variants.h" + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, PL4 */ + /* PL2 values are for performance configuration */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 55000, 55000, 123000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 55000, 55000, 123000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000, 140000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000, 140000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 }, +}; + +WEAK_DEV_PTR(dptf_policy); +void variant_update_power_limits(void) +{ + const struct device *policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + struct drivers_intel_dptf_config *config = config_of(policy_dev); + + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + u8 tdp = get_cpu_tdp(); + + for (size_t i = 0; i < ARRAY_SIZE(limits); i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + struct dptf_power_limits *settings = &config->controls.power_limits; + config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config = conf->power_limits_config; + settings->pl1.min_power = limits[i].pl1_min_power; + settings->pl1.max_power = limits[i].pl1_max_power; + settings->pl2.min_power = limits[i].pl2_min_power; + settings->pl2.max_power = limits[i].pl2_max_power; + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + MILLIWATTS_TO_WATTS); + printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power, + limits[i].pl4_power); + } + } +} + +void variant_devtree_update(void) +{ + variant_update_power_limits(); +} diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c new file mode 100644 index 0000000..33875c1 --- /dev/null +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <soc/meminit.h> +#include "variants.h" +#include "board_id.h" + +#define SPD_ID_MASK 0x7 + +static size_t get_spd_index(void) +{ + uint8_t board_id = get_board_id(); + size_t spd_index; + + printk(BIOS_INFO, "board id is 0x%x\n", board_id); + + spd_index = board_id & SPD_ID_MASK; + + printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index); + return spd_index; +} + +/* + * ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's + * 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are + * connected on the platform, an external differential buffer chip needs to be placed at + * the platform level. + * + * GEN3_EXTERNAL_CLOCK_BUFFER Kconfig is selected for ADL-P RVP (not applicable for + * ADL-M/N RVP) + * + * CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete + * buffer for further distribution to platform. + */ +static void configure_external_clksrc(FSP_M_CONFIG *m_cfg) +{ + for (unsigned int i = CONFIG_MAX_PCIE_CLOCK_SRC; i < CONFIG_MAX_PCIE_CLOCK_REQ; i++) + m_cfg->PcieClkSrcUsage[i] = CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER; +} + +void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + const struct mb_cfg *mem_config = variant_memory_params(); + int board_id = get_board_id(); + const bool half_populated = false; + + const struct mem_spd memory_down_spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, + .cbfs_index = get_spd_index(), + }; + + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + .addr_dimm[1] = 0x51, + }, + [1] = { + .addr_dimm[0] = 0x52, + .addr_dimm[1] = 0x53, + }, + }, + }; + + switch (board_id) { + case ADL_P_DDR5_1: + memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated); + break; + case ADL_P_DDR5_2: + memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated); + break; + default: + die("Unknown board id = 0x%x\n", board_id); + break; + } + + if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER)) + configure_external_clksrc(m_cfg); +} diff --git a/src/mainboard/prodrive/atlas/spd/Makefile.inc b/src/mainboard/prodrive/atlas/spd/Makefile.inc new file mode 100644 index 0000000..61140c3 --- /dev/null +++ b/src/mainboard/prodrive/atlas/spd/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES += empty # 0b000 +SPD_SOURCES += adlrvp_ddr5_mr # 0b001 diff --git a/src/mainboard/prodrive/atlas/spd/adlrvp_ddr5_mr.spd.hex b/src/mainboard/prodrive/atlas/spd/adlrvp_ddr5_mr.spd.hex new file mode 100644 index 0000000..80ef521 --- /dev/null +++ b/src/mainboard/prodrive/atlas/spd/adlrvp_ddr5_mr.spd.hex @@ -0,0 +1,32 @@ +30 08 12 03 04 00 20 62 00 00 00 00 60 00 00 00 +00 00 00 00 A1 01 E8 03 72 15 00 00 00 00 1E 41 +1E 41 1E 41 00 7D 1E BE 30 75 27 01 A0 00 82 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 47 AE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +08 00 C2 C4 80 00 80 B3 80 11 00 00 00 00 00 00 +00 00 80 B3 80 11 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 0F 10 00 01 01 22 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 9C AD +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/prodrive/atlas/spd/empty.spd.hex b/src/mainboard/prodrive/atlas/spd/empty.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/prodrive/atlas/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/prodrive/atlas/variants.h b/src/mainboard/prodrive/atlas/variants.h new file mode 100644 index 0000000..43e3f4b --- /dev/null +++ b/src/mainboard/prodrive/atlas/variants.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <stdint.h> + +enum adl_boardid { + /* ADL-P DDR5 RVPs */ + ADL_P_DDR5_1 = 0x12, + ADL_P_DDR5_2 = 0x16, +}; + +/* Functions to configure GPIO as per variant schematics */ +void variant_configure_gpio_pads(void); +void variant_configure_early_gpio_pads(void); + +size_t variant_memory_sku(void); +const struct mb_cfg *variant_memory_params(void); + +/* Modify devictree settings during ramstage */ +void variant_devtree_update(void); +struct cpu_power_limits { + uint16_t mchid; + u8 cpu_tdp; + unsigned int pl1_min_power; + unsigned int pl1_max_power; + unsigned int pl2_min_power; + unsigned int pl2_max_power; + unsigned int pl4_power; +}; +/* Modify Power Limit devictree settings during ramstage */ +void variant_update_power_limits(void); + +#endif /*__BASEBOARD_VARIANTS_H__ */
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Sheng Lean Tan (Code Review)