Change in coreboot[master]: soc/intel/common/block/fast_spi: Refactor ROM caching implementation

[Subrata Banik (Code Review)]

Attention is currently required from: Subrata Banik, Angel Pons, Nick Vaccaro, Kane Chen, Werner Zeh.
Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Kane Chen, Werner Zeh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63221

to look at the new patch set (#2).

Change subject: soc/intel/common/block/fast_spi: Refactor ROM caching implementation
......................................................................

soc/intel/common/block/fast_spi: Refactor ROM caching implementation

This patch removes different implementation to cache the SPI ROM between
early and later boot stage where SPI ROM caching doesn't need even
advanced implementation like `mtrr_use_temp_range()` as SPI ROM ranage
is always mapped to below 4GB hence, simple `set_var_mtrr()` function
can be sufficient without any additional complexity.

BUG=b:225766934
TEST=Calling into `fast_spi_cache_bios_region()` from ramstage is able
to update the temporary variable range MTRRs and showed ~44ms of boot
time savings as below:

Before:
  90:starting to load payload                    1,084,052 (14)
  15:starting LZMA decompress (ignore for x86)   1,084,121 (68)
  16:finished LZMA decompress (ignore for x86)   1,140,742 (56,620)

After:
  90:starting to load payload                    1,090,433 (14)
  15:starting LZMA decompress (ignore for x86)   1,090,650 (217)
  16:finished LZMA decompress (ignore for x86)   1,102,896 (12,245)

Signed-off-by: Subrata Banik 
Change-Id: I43973b45dc6d032cfcc920eeb36b37fe027e6e8e
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
1 file changed, 15 insertions(+), 20 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63221/2