Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID

[Jes Klinke (Code Review)]

Jes Klinke has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63158 )

Change subject: tpm: Accept Google Ti50 TPM DID:VID
......................................................................

tpm: Accept Google Ti50 TPM DID:VID

A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow
the same protocol as the earlier design.

Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986
Signed-off-by: Jes B. Klinke 
---
M src/drivers/crb/tis.c
M src/drivers/i2c/tpm/cr50.c
M src/drivers/spi/tpm/tpm.c
3 files changed, 14 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/63158/1

diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c
index 800d145..47924ee 100644
--- a/src/drivers/crb/tis.c
+++ b/src/drivers/crb/tis.c
@@ -17,6 +17,7 @@
    const char *device_name;
 } dev_map[] = {
    {0x1ae0, 0x0028, "CR50"},
+	{0x6666, 0x50a4, "TI50"},
    {0xa13a, 0x8086, "Intel iTPM"}
 };

diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c
index 7eb066d..ffb0762 100644
--- a/src/drivers/i2c/tpm/cr50.c
+++ b/src/drivers/i2c/tpm/cr50.c
@@ -36,6 +36,7 @@
 #define CR50_TIMEOUT_NOIRQ_MS	20	/* Timeout for TPM ready without IRQ */
 #define CR50_TIMEOUT_IRQ_MS	100	/* Timeout for TPM ready with IRQ */
 #define CR50_DID_VID		0x00281ae0L
+#define TI50_DID_VID		0x504a6666L

struct tpm_inf_dev {
    int bus;
@@ -455,7 +456,7 @@
    	rc = cr50_i2c_read(TPM_DID_VID(0), (uint8_t *)did_vid, 4);

/* Exit once DID and VID verified */
-		if (!rc && (*did_vid == CR50_DID_VID)) {
+		if (!rc && (*did_vid == CR50_DID_VID || *did_vid == TI50_DID_VID)) {
    		printk(BIOS_INFO, "done! DID_VID 0x%08x\n", *did_vid);
    		return 0;
    	}
diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c
index 43fd933..af79990 100644
--- a/src/drivers/spi/tpm/tpm.c
+++ b/src/drivers/spi/tpm/tpm.c
@@ -419,6 +419,7 @@
 /* Device/vendor ID values of the TPM devices this driver supports. */
 static const uint32_t supported_did_vids[] = {
    0x00281ae0,  /* H1 based Cr50 security chip. */
+	0x504a6666,  /* H1 based Ti50 security chip. */
    0x0000104a   /* ST33HTPH2E32 */
 };

@@ -507,6 +508,16 @@
    		cr50_set_board_cfg();
    	}
    }
+	/* Do some ti50-specific things here. */
+	if (CONFIG(TPM_CR50) && tpm_info.vendor_id == 0x6666 && tpm_info.device_id == 0x504a) {
+		struct cr50_firmware_version ver;
+
+		if (tpm_first_access_this_boot()) {
+			/* This is called for the side-effect of printing the firmware version
+			   string */
+			cr50_get_firmware_version(&ver);
+		}
+	}
    return 0;
 }