[S] Change in coreboot[main]: mb/google/brya/var/dochi: Update overridetree for type c1

[Morris Hsu (Code Review)]

Morris Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79343?usp=email )

Change subject: mb/google/brya/var/dochi: Update overridetree for type c1
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mb/google/brya/var/dochi: Update overridetree for type c1

Update overridetree to correct type c1 does not show HDMI.

BUG=b:299570339
TEST=emerge-brya coreboot chromeos-bootimage

Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba
Signed-off-by: Morris Hsu 
---
M src/mainboard/google/brya/variants/dochi/overridetree.cb
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/79343/1

diff --git a/src/mainboard/google/brya/variants/dochi/overridetree.cb b/src/mainboard/google/brya/variants/dochi/overridetree.cb
index cc74f8d..19ace7b 100644
--- a/src/mainboard/google/brya/variants/dochi/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dochi/overridetree.cb
@@ -18,14 +18,14 @@

# SOC Aux orientation override:
    # This is a bitfield that corresponds to up to 4 TCSS ports.
-	# Bits (0,1) allocated for TCSS Port1 configuration, Bits (2,3)for TCSS Port2.
-	# TcssAuxOri = 0101b
-	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports, otherwise is "0"
-	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+	# Bits (0,1) allocated for TCSS Port1 configuration, Bits (4,5)for TCSS Port3.
+	# TcssAuxOri = 010001b
+	# Bit0,Bit4 set to "1" indicates no retimer on USBC Ports, otherwise is "0"
+	# Bit1,Bit5 set to "0" indicates Aux lines are not swapped on the
    # motherboard to USBC connector
-	register "tcss_aux_ori" = "0x5"
+	register "tcss_aux_ori" = "0x11"
    register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
-	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
+	register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"

register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Disable USB2 Port 1
    register "usb2_ports[3]" = "USB2_PORT_EMPTY"	        # Disable USB2 Port 3