Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46485 )
Change subject: mb/intel/adlrvp: Add support for DDR5 memory ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c:
https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp/... PS7, Line 62: .rcomp_targets = {50, 30, 30, 30, 27},
Sure Angel. Nice feedback. […]
No, I meant to have something like:
const uint16_t rcomp_targets_ddr5_p[5] = {50, 30, 30, 30, 27};
Then, one should be able to simply use the array as initializer:
.rcomp_targets = rcomp_targets_ddr5_p,
I haven't tested this, though. I would also like to ensure these Rcomp targets are reasonable defaults. I can try to do this for SKL and CFL as an example, since I know the platforms better. I mean, I've desoldered measured the Rcomp resistors on a SKL-S CPU 😄
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Angel Pons (Code Review)