Change in coreboot[master]: mb/google/brya: Move GPE configuration to baseboard/devicetree.cb

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51298 )

Change subject: mb/google/brya: Move GPE configuration to baseboard/devicetree.cb
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mb/google/brya: Move GPE configuration to baseboard/devicetree.cb

This change moves GPE configuration from brya0/overridetree.cb to
baseboard/devicetree.cb since all variants will end up using the same
configuration.

TEST=Verified using "abuild -p none -t google/brya -b brya0
--timeless" that coreboot.rom generated with and without this change
is the same.

Change-Id: Ie31bf2bf8a91da82fca77c78fb0a735a2645de55
Signed-off-by: Furquan Shaikh 
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
M src/mainboard/google/brya/variants/brya0/overridetree.cb
2 files changed, 5 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/51298/1

diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index d82a9eb..7fe2fe1 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -3,6 +3,11 @@
    	device lapic 0 on end
    end

+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_E"
+	register "pmc_gpe0_dw2" = "GPP_F"
+
    # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
    register "gen1_dec" = "0x00fc0801"
    register "gen2_dec" = "0x000c0201"
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index aa5dc8f..a0d34ca 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -1,8 +1,4 @@
 chip soc/intel/alderlake
-	register "pmc_gpe0_dw0" = "GPP_A"
-	register "pmc_gpe0_dw1" = "GPP_E"
-	register "pmc_gpe0_dw2" = "GPP_F"
-
    register "SaGv" = "SaGv_Disabled"

register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A MLB Port