Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 )

Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
......................................................................

Patch Set 2:
> Patch Set 1:
> > Patch Set 1:
> >
> > There are 0 mainboards that use this feature right now, and you want to enable it for all of those platforms? Have you tested it on any?
>
> Heh, I did not say this shall be merged without any testing ;) I just didn't have the time earlier to add all relevant people.
>
> However, this power gating feature - to my knowlege - doesn't depend on board design, thus shouldn't cause any issues. Hopefully.
>
> @all Would be great if you could test this on your boards and give feedback. Feel free to add people, if you think someone is missing. Thanks!

Gotcha, I will test on what I have.