Change in coreboot[master]: soc/amd/cezanne: add GNB IOAPIC support

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Raul Rangel has uploaded a new patch set (#3) to the change originally created by Felix Held. ( https://review.coreboot.org/c/coreboot/+/52905 )

Change subject: soc/amd/cezanne: add GNB IOAPIC support
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soc/amd/cezanne: add GNB IOAPIC support

To configure and enable the IOAPIC in the graphics and northbridge (GNB)
container, FSP needs to write an undocumented register, so pass the GNB
IOAPIC MMIO base address to make it show up at that address.

BUG=b:187083211
TEST=Boot guybrush and see IO-APIC initialized
IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23
IOAPIC[1]: apic_id 17, version 33, address 0xfec01000, GSI 24-55

Signed-off-by: Felix Held 
Signed-off-by: Raul E Rangel 
Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e
---
M src/soc/amd/cezanne/acpi.c
M src/soc/amd/cezanne/fsp_m_params.c
M src/soc/amd/cezanne/include/soc/iomap.h
M src/soc/amd/cezanne/root_complex.c
4 files changed, 29 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/52905/3