[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Keith Hui (Code Review)]

Attention is currently required from: Keith Hui.

Hello Bill XIE, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85413?usp=email

to look at the new patch set (#3).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

Bill Xie documented in his initial code drop that he was unsuccessful
in reproducing all the PCIe configurations possible with vendor
firmware. I obtained a boardview to this board and have identified the
PCIe lane topology and the required control signals.

There are PCIe slot presence signals wired to GPIOs 34,20,7 for
PCIEX1_1,PCIEX1_2,PCIEX16_3 respectively, the last one only sense the
presence of a PCIe x4 or larger card. PCIe lanes 1-4 are routed by way
of three ASM1440 2-way switches controlled by GP54-GP56 on NCT6779D
super I/O chip. PCIe lanes 5-8 are fixed.

With these details, it is now possible to attempt to reproduce all the
vendor PCIe configurations.

1. Change GPIO20 of PCH to GPIO input so coreboot can detect a
card inserted into PCIEX1_2.
2. Add an nvram option to force PCIe lane 4 to serve ASM1061 and its
two SATA 6Gbps ports. Another one needs to be added later to enable
users to allocate all lanes to PCIEX16_3 and make it x4.
3. Add code to bootblock to check the PCHSTRP9 soft strap and whether
(1) is true. There is a sanity check to warn of a PCIe configuration
that is not valid on this board.
4. Based on (1) and (2), program SIO GPIO5 as appropriate. Remove all
GPIO5 settings from devicetree so this code has full control.

Changing PCIEX16_3 from x1 to x4 (and vice versa) requires changing
PCHSTRP9 in the SPI flash descriptor. How coreboot can manage this
is TBD.

This is based on boardview only, and is untested because I have
no hardware.

Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c
Signed-off-by: Keith Hui 
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default
M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout
M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
M src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c
M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb
5 files changed, 113 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85413/3