Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
nb/intel/haswell: Implement proper backlight PWM config
Further backport the backlight-PWM handling from Skylake. Beside configuring the PWM frequency in Hz, we also use the PCH's logic for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux would toggle it anyway and that might confuse our ASL code.
We assume that the 183Hz value that was set before for Slippy variants was overridden with 200Hz like it was for the Broadwell Chromebooks. So we set 200Hz for them in the devicetrees. The calculated value for the T440p of 220Hz seems sane.
Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/slippy/variants/falco/devicetree.cb M src/mainboard/google/slippy/variants/leon/devicetree.cb M src/mainboard/google/slippy/variants/peppy/devicetree.cb M src/mainboard/google/slippy/variants/wolf/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c 8 files changed, 44 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39769/1
diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/variants/falco/devicetree.cb index f2a9520..2d07683 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/variants/falco/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb index 8951e99..4cf1e72 100644 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ b/src/mainboard/google/slippy/variants/leon/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb index 6451d95..7bb18c0 100644 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb index 2cad23b..159d51a 100644 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 1022e77..621159a 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -12,7 +12,7 @@ register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "2000" - register "gpu_pch_backlight" = "0x12ba12ba" + register "gpu_pch_backlight_pwm_hz" = "220" device cpu_cluster 0x0 on chip cpu/intel/haswell register "c1_acpower" = "1" diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 06ce371..5e631cf 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -107,7 +107,4 @@ depends on VBOOT default "mrc.bin"
-config INTEL_GMA_BCLV_OFFSET - default 0x48254 - endif diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index cfc2884..d7ef27d 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -36,8 +36,11 @@ u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
- u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ - u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + unsigned int gpu_pch_backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } gpu_pch_backlight_polarity;
bool gpu_ddi_e_connected;
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index eed6740..873c7ea 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -347,14 +347,36 @@ gtt_write(PCH_PP_DIVISOR, reg32); }
- /* Enable Backlight if needed */ - if (conf->gpu_cpu_backlight) { - gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); - gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); - } - if (conf->gpu_pch_backlight) { - gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); - gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); + /* Enforce the PCH PWM function, as so does Linux. + The CPU PWM controls are disabled after reset. */ + if (conf->gpu_pch_backlight_pwm_hz) { + /* Reference clock is either 24MHz or 135MHz. We can choose + either a 16 or a 128 step increment. Use 16 if we would + have less than 100 steps otherwise. */ + const unsigned int refclock = CONFIG(INTEL_LYNXPOINT_LP) + ? 24 * 1000 * 1000 + : 135 * 1000 * 1000; + const unsigned int hz_limit = refclock / 128 / 100; + unsigned int pwm_increment, pwm_period; + u32 south_chicken2; + + south_chicken2 = gtt_read(SOUTH_CHICKEN2); + if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + pwm_increment = 16; + south_chicken2 |= 1 << 5; + } else { + pwm_increment = 128; + south_chicken2 &= ~(1 << 5); + } + gtt_write(SOUTH_CHICKEN2, south_chicken2); + + pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + /* Start with a 50% duty cycle. */ + gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); + + gtt_write(BLC_PWM_PCH_CTL1, + (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); }
/* Get display,pipeline,and DDI registers into a basic sane state */
Hello build bot (Jenkins), Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39769
to look at the new patch set (#2).
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
nb/intel/haswell: Implement proper backlight PWM config
Further backport the backlight-PWM handling from Skylake. Beside configuring the PWM frequency in Hz, we also use the PCH's logic for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux would toggle it anyway and that might confuse our ASL code.
We assume that the 183Hz value that was set before for Slippy variants was overridden with 200Hz like it was for the Broadwell Chromebooks. So we set 200Hz for them in the devicetrees. The calculated value for the T440p of 220Hz seems sane.
Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/slippy/variants/falco/devicetree.cb M src/mainboard/google/slippy/variants/leon/devicetree.cb M src/mainboard/google/slippy/variants/peppy/devicetree.cb M src/mainboard/google/slippy/variants/wolf/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c 8 files changed, 44 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39769/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39769/4/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/gma.c:
https://review.coreboot.org/c/coreboot/+/39769/4/src/northbridge/intel/haswe... PS4, Line 359: refclock / 128 / 100 Which of the two divisions goes first?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39769/4/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/gma.c:
https://review.coreboot.org/c/coreboot/+/39769/4/src/northbridge/intel/haswe... PS4, Line 359: refclock / 128 / 100
Which of the two divisions goes first?
With the exception of assignments, all binary operators in C are left-associative, i.e. you can read this from left to right like conventional math (well, the math I learned, don't know how international it is).
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39769/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39769/4//COMMIT_MSG@15 PS4, Line 15: variants was overridden with 200Hz like it was for the Broadwell Where was it overridden? By Linux?
https://review.coreboot.org/c/coreboot/+/39769/4/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/gma.c:
https://review.coreboot.org/c/coreboot/+/39769/4/src/northbridge/intel/haswe... PS4, Line 370: } Please add some debug messages, or is there another way to deduce the settings from the coreboot log?
Hello build bot (Jenkins), Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39769
to look at the new patch set (#5).
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
nb/intel/haswell: Implement proper backlight PWM config
Further backport the backlight-PWM handling from Skylake. Beside configuring the PWM frequency in Hz, we also use the PCH's logic for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux would toggle it anyway and that might confuse our ASL code.
We assume that the 183Hz value that was set before for Slippy variants was overridden by Linux with the 200Hz VBT value, like it was for the Broadwell Chromebooks. So we set 200Hz for them in the devicetrees. The calculated value for the T440p of 220Hz seems sane and also matches the VBT.
Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/slippy/variants/falco/devicetree.cb M src/mainboard/google/slippy/variants/leon/devicetree.cb M src/mainboard/google/slippy/variants/peppy/devicetree.cb M src/mainboard/google/slippy/variants/wolf/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c 7 files changed, 44 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39769/5
Hello build bot (Jenkins), Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39769
to look at the new patch set (#6).
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
nb/intel/haswell: Implement proper backlight PWM config
Further backport the backlight-PWM handling from Skylake. Beside configuring the PWM frequency in Hz, we also use the PCH's logic for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux would toggle it anyway and that might confuse our ASL code.
We assume that the 183Hz value that was set before for Slippy variants was overridden by Linux with the 200Hz VBT value, like it was for the Broadwell Chromebooks. So we set 200Hz for them in the devicetrees. The calculated value for the T440p of 220Hz seems sane and also matches the VBT.
Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/slippy/variants/falco/devicetree.cb M src/mainboard/google/slippy/variants/leon/devicetree.cb M src/mainboard/google/slippy/variants/peppy/devicetree.cb M src/mainboard/google/slippy/variants/wolf/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c 7 files changed, 48 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39769/6
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
Patch Set 6: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/39769/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39769/6//COMMIT_MSG@14 PS6, Line 14: e assume that the 183Hz value that was set before for Slippy : variants was overridden by Linux with the 200Hz VBT value, like : it was for the Broadwell Chromebooks. So we set 200Hz for them : in the devicetrees. The calculated value for the T440p of 220Hz : seems sane and also matches the VBT. I can't find the history in our internal bug database so I'm going to assume this is correct.
https://review.coreboot.org/c/coreboot/+/39769/6/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/gma.c:
https://review.coreboot.org/c/coreboot/+/39769/6/src/northbridge/intel/haswe... PS6, Line 365: 1 << 5 maybe add a #define for this?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
Patch Set 6: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/39769/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39769/4//COMMIT_MSG@15 PS4, Line 15: variants was overridden with 200Hz like it was for the Broadwell
Where was it overridden? By Linux?
Done
https://review.coreboot.org/c/coreboot/+/39769/4/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/gma.c:
https://review.coreboot.org/c/coreboot/+/39769/4/src/northbridge/intel/haswe... PS4, Line 370: }
Please add some debug messages, or is there another way to deduce the settings from the coreboot log […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39769/4/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/gma.c:
https://review.coreboot.org/c/coreboot/+/39769/4/src/northbridge/intel/haswe... PS4, Line 359: refclock / 128 / 100
With the exception of assignments, all binary operators in C are left-associative, […]
I tend to prefer "refclock / (128 * 100)", but I'm more used to writing math on treeware:
refclock ------------- 128 * 100
In any case, not a big deal.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39769/6/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/gma.c:
https://review.coreboot.org/c/coreboot/+/39769/6/src/northbridge/intel/haswe... PS6, Line 365: 1 << 5
maybe add a #define for this?
Angel, what do you think? You found it in the documentation; do you think it would have been easier to review with a name?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39769/6/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/gma.c:
https://review.coreboot.org/c/coreboot/+/39769/6/src/northbridge/intel/haswe... PS6, Line 365: 1 << 5
Angel, what do you think? You found it in the documentation; do you think […]
Well, i915 calls it LPT_PWM_GRANULARITY... Since we also use the SOUTH_CHICKEN2 name from i915, it makes sense to use a #define
Hello build bot (Jenkins), Paul Menzel, Duncan Laurie, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39769
to look at the new patch set (#7).
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
nb/intel/haswell: Implement proper backlight PWM config
Further backport the backlight-PWM handling from Skylake. Beside configuring the PWM frequency in Hz, we also use the PCH's logic for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux would toggle it anyway and that might confuse our ASL code.
We assume that the 183Hz value that was set before for Slippy variants was overridden by Linux with the 200Hz VBT value, like it was for the Broadwell Chromebooks. So we set 200Hz for them in the devicetrees. The calculated value for the T440p of 220Hz seems sane and also matches the VBT.
Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/drivers/intel/gma/i915_reg.h M src/mainboard/google/slippy/variants/falco/devicetree.cb M src/mainboard/google/slippy/variants/leon/devicetree.cb M src/mainboard/google/slippy/variants/peppy/devicetree.cb M src/mainboard/google/slippy/variants/wolf/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c 8 files changed, 49 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39769/7
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39769/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39769/6//COMMIT_MSG@14 PS6, Line 14: e assume that the 183Hz value that was set before for Slippy : variants was overridden by Linux with the 200Hz VBT value, like : it was for the Broadwell Chromebooks. So we set 200Hz for them : in the devicetrees. The calculated value for the T440p of 220Hz : seems sane and also matches the VBT.
I can't find the history in our internal bug database so I'm going to assume this is correct.
Ack, I guess
https://review.coreboot.org/c/coreboot/+/39769/6/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/gma.c:
https://review.coreboot.org/c/coreboot/+/39769/6/src/northbridge/intel/haswe... PS6, Line 365: 1 << 5
Well, i915 calls it LPT_PWM_GRANULARITY... […]
Done
Now I wonder if we should try to fully synchronize `i915_reg.h` from time to time. Definitely a candidate for BUILD_TIMELES checks.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
Patch Set 7: Code-Review+2
Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
nb/intel/haswell: Implement proper backlight PWM config
Further backport the backlight-PWM handling from Skylake. Beside configuring the PWM frequency in Hz, we also use the PCH's logic for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux would toggle it anyway and that might confuse our ASL code.
We assume that the 183Hz value that was set before for Slippy variants was overridden by Linux with the 200Hz VBT value, like it was for the Broadwell Chromebooks. So we set 200Hz for them in the devicetrees. The calculated value for the T440p of 220Hz seems sane and also matches the VBT.
Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3 Signed-off-by: Nico Huber nico.h@gmx.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/39769 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/drivers/intel/gma/i915_reg.h M src/mainboard/google/slippy/variants/falco/devicetree.cb M src/mainboard/google/slippy/variants/leon/devicetree.cb M src/mainboard/google/slippy/variants/peppy/devicetree.cb M src/mainboard/google/slippy/variants/wolf/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c 8 files changed, 49 insertions(+), 24 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index e0bf142..38ea72a 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -3580,6 +3580,7 @@ #define SOUTH_CHICKEN2 0xc2004 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) +#define LPT_PWM_GRANULARITY (1<<5) #define DPLS_EDP_PPS_FIX_DIS (1<<0)
#define _FDI_RXA_CHICKEN 0xc200c diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/variants/falco/devicetree.cb index f2a9520..2d07683 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/variants/falco/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb index 8951e99..4cf1e72 100644 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ b/src/mainboard/google/slippy/variants/leon/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb index 6451d95..7bb18c0 100644 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb index 2cad23b..159d51a 100644 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 1022e77..1f84007 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.ndid" = "3" - register "gpu_cpu_backlight" = "0x12ba12ba" register "gpu_ddi_e_connected" = "1" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" @@ -12,7 +11,7 @@ register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "2000" - register "gpu_pch_backlight" = "0x12ba12ba" + register "gpu_pch_backlight_pwm_hz" = "220" device cpu_cluster 0x0 on chip cpu/intel/haswell register "c1_acpower" = "1" diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index cfc2884..d7ef27d 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -36,8 +36,11 @@ u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
- u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ - u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + unsigned int gpu_pch_backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } gpu_pch_backlight_polarity;
bool gpu_ddi_e_connected;
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index eed6740..65c5cf3 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -12,6 +12,7 @@ * GNU General Public License for more details. */
+#include <commonlib/helpers.h> #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -347,14 +348,39 @@ gtt_write(PCH_PP_DIVISOR, reg32); }
- /* Enable Backlight if needed */ - if (conf->gpu_cpu_backlight) { - gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); - gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); - } - if (conf->gpu_pch_backlight) { - gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); - gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); + /* Enforce the PCH PWM function, as so does Linux. + The CPU PWM controls are disabled after reset. */ + if (conf->gpu_pch_backlight_pwm_hz) { + /* Reference clock is either 24MHz or 135MHz. We can choose + either a 16 or a 128 step increment. Use 16 if we would + have less than 100 steps otherwise. */ + const unsigned int refclock = CONFIG(INTEL_LYNXPOINT_LP) ? 24*MHz : 135*MHz; + const unsigned int hz_limit = refclock / 128 / 100; + unsigned int pwm_increment, pwm_period; + u32 south_chicken2; + + south_chicken2 = gtt_read(SOUTH_CHICKEN2); + if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + pwm_increment = 16; + south_chicken2 |= LPT_PWM_GRANULARITY; + } else { + pwm_increment = 128; + south_chicken2 &= ~LPT_PWM_GRANULARITY; + } + gtt_write(SOUTH_CHICKEN2, south_chicken2); + + pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + printk(BIOS_INFO, + "GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n", + refclock / MHz, pwm_increment, pwm_period, + DIV_ROUND_CLOSEST(refclock, pwm_increment * pwm_period)); + + /* Start with a 50% duty cycle. */ + gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); + + gtt_write(BLC_PWM_PCH_CTL1, + (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); }
/* Get display,pipeline,and DDI registers into a basic sane state */
-
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