Change in ...coreboot[master]: sdm845: Add QCLib to RomStage to perform IP init

[T.Michael Turney (Code Review)]

Hello T Michael Turney, Julius Werner, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/25208

to look at the new patch set (#77).

Change subject: sdm845: Add QCLib to RomStage to perform IP init
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sdm845: Add QCLib to RomStage to perform IP init

CB acts as I/O handler for QCLib (e.g. DDR training data)
This interface allows bi-directional data flow between
CB and QCLib
Tested and working interfaces:
 DDR Training data
 QCLib serial console output
 DDR Information (base & size)
 limits cfg data
TEST=build & run

Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1
Signed-off-by: T Michael Turney 
---
M src/mainboard/google/cheza/chromeos.fmd
M src/mainboard/google/cheza/romstage.c
M src/soc/qualcomm/sdm845/Makefile.inc
M src/soc/qualcomm/sdm845/include/soc/memlayout.ld
M src/soc/qualcomm/sdm845/include/soc/mmu.h
M src/soc/qualcomm/sdm845/include/soc/symbols.h
M src/soc/qualcomm/sdm845/mmu.c
A src/soc/qualcomm/sdm845/qclib.c
M src/soc/qualcomm/sdm845/soc.c
9 files changed, 84 insertions(+), 22 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/25208/77