Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82124?usp=email )
Change subject: spd.h: Move enum ddr4_module_type to ddr4.h ......................................................................
spd.h: Move enum ddr4_module_type to ddr4.h
Move specific enum ddr4_module_type to <device/dram/ddr4.h>.
Change-Id: I33afccb768eaee94cc1cd947eb0ddbe15c2831bd Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/device/dram/ddr3.c M src/device/dram/ddr4.c M src/device/dram/spd.c M src/include/device/dram/ddr3.h M src/include/device/dram/ddr4.h M src/include/spd.h M src/northbridge/intel/haswell/native_raminit/raminit_native.h M src/northbridge/intel/sandybridge/raminit.c M src/soc/intel/baytrail/romstage/raminit.c M tests/lib/dimm_info_util-test.c 10 files changed, 30 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/82124/1
diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 1fa3f4c..8d2752b 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -97,7 +97,7 @@ * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was * detected. */ -int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd) +int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd) { int ret; u16 crc, spd_crc; @@ -122,7 +122,7 @@ dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3; dimm->dimm_type = spd[3] & 0xf;
- crc = spd_ddr3_calc_crc(spd, sizeof(spd_raw_data)); + crc = spd_ddr3_calc_crc(spd, sizeof(spd_ddr3_raw_data)); /* Compare with the CRC in the SPD */ spd_crc = (spd[127] << 8) + spd[126]; /* Verify the CRC is correct */ @@ -390,7 +390,7 @@ * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was * detected. */ -int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd, +int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd, enum ddr3_xmp_profile profile) { int ret; diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 9a8c5eb..6ccef72 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -70,7 +70,7 @@ {.type = BLOCK_3, 384, 128, 0} };
-static bool verify_block(const spd_block *block, spd_raw_data spd) +static bool verify_block(const spd_block *block, spd_ddr4_raw_data spd) { uint16_t crc, spd_crc;
@@ -136,7 +136,7 @@ * SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD * SPD_STATUS_CRC_ERROR -- checksum mismatch */ -int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd) +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd) { u8 reg8; u8 bus_width, sdram_width; diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c index c4ccfee..ae55ee5 100644 --- a/src/device/dram/spd.c +++ b/src/device/dram/spd.c @@ -2,6 +2,7 @@
#include <device/dram/ddr2.h> #include <device/dram/ddr3.h> +#include <device/dram/ddr4.h> #include <device/dram/ddr5.h> #include <device/dram/spd.h> #include <spd.h> @@ -113,18 +114,18 @@ struct spd_info *info) { switch (module_type) { - case DDR4_SPD_RDIMM: - case DDR4_SPD_MINI_RDIMM: + case SPD_DDR4_DIMM_TYPE_RDIMM: + case SPD_DDR4_DIMM_TYPE_MINI_RDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; break; - case DDR4_SPD_UDIMM: - case DDR4_SPD_MINI_UDIMM: + case SPD_DDR4_DIMM_TYPE_UDIMM: + case SPD_DDR4_DIMM_TYPE_MINI_UDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; break; - case DDR4_SPD_SODIMM: - case DDR4_SPD_72B_SO_UDIMM: + case SPD_DDR4_DIMM_TYPE_SO_DIMM: + case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM: info->form_factor = MEMORY_FORMFACTOR_SODIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 6efe049..65977b4 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -153,15 +153,15 @@ DDR3_XMP_PROFILE_2 = 1, };
-typedef u8 spd_raw_data[256]; +typedef u8 spd_ddr3_raw_data[SPD_SIZE_MAX_DDR3];
u16 spd_ddr3_calc_crc(u8 *spd, int len); u16 spd_ddr3_calc_unique_crc(u8 *spd, int len); -int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data); +int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd_data); int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type); void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm); int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, - spd_raw_data spd, + spd_ddr3_raw_data spd, enum ddr3_xmp_profile profile); enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected_freq, diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index 7210212..da7359a 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -64,9 +64,9 @@ bool ecc_extension; };
-typedef u8 spd_raw_data[512]; +typedef u8 spd_ddr4_raw_data[SPD_SIZE_MAX_DDR4];
-int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd); +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd);
enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, diff --git a/src/include/spd.h b/src/include/spd.h index b456680..ff0cd64 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -201,20 +201,6 @@ #define SPD_ECC_8BIT (1<<3) #define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
-/* Byte 3 [3:0]: DDR4 Module type information */ -enum ddr4_module_type { - DDR4_SPD_RDIMM = 0x01, - DDR4_SPD_UDIMM = 0x02, - DDR4_SPD_SODIMM = 0x03, - DDR4_SPD_LRDIMM = 0x04, - DDR4_SPD_MINI_RDIMM = 0x05, - DDR4_SPD_MINI_UDIMM = 0x06, - DDR4_SPD_72B_SO_RDIMM = 0x08, - DDR4_SPD_72B_SO_UDIMM = 0x09, - DDR4_SPD_16B_SO_DIMM = 0x0c, - DDR4_SPD_32B_SO_RDIMM = 0x0d, -}; - enum lpx_module_type { LPX_SPD_LPDIMM = 0x07, LPX_SPD_NONDIMM = 0x0e, diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h index 1a07939..acb4c8b 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -33,7 +33,7 @@ };
struct raminit_dimm_info { - spd_raw_data raw_spd; + spd_drr3_raw_data raw_spd; struct dimm_attr_ddr3_st data; uint8_t spd_addr; bool valid; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 2b59b9e..2a4eae5 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -123,7 +123,7 @@ }
/* Return CRC16 match for all SPDs */ -static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) +static int verify_crc16_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl) { int channel, slot, spd_slot; int match = 1; @@ -132,13 +132,13 @@ for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; match &= ctrl->spd_crc[channel][slot] == - spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data)); } } return match; }
-static void read_spd(spd_raw_data *spd, u8 addr, bool id_only) +static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only) { int j; if (id_only) { @@ -150,7 +150,7 @@ } }
-static void mainboard_get_spd(spd_raw_data *spd, bool id_only) +static void mainboard_get_spd(spd_ddr3_raw_data *spd, bool id_only) { const struct northbridge_intel_sandybridge_config *cfg = config_of_soc(); unsigned int i; @@ -192,7 +192,7 @@ } /* CONFIG(HAVE_SPD_IN_CBFS) */ }
-static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) +static void dram_find_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl) { int dimms = 0, ch_dimms; int channel, slot, spd_slot; @@ -254,7 +254,7 @@
/* Fill in CRC16 for MRC cache */ ctrl->spd_crc[channel][slot] = - spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data));
if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { /* Mark DIMM as invalid */ @@ -339,7 +339,7 @@ { int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; - spd_raw_data spds[4]; + spd_ddr3_raw_data spds[4]; size_t mrc_size; ramctr_timing *ctrl_cached = NULL;
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index b64364b..6244072 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -59,7 +59,7 @@ enum spd_status status;
/* Decode into dimm_attr struct */ - status = spd_decode_ddr3(&dimm, *(spd_raw_data *)dram_data); + status = spd_decode_ddr3(&dimm, *(spd_ddr3_raw_data *)dram_data);
/* Some SPDs have bad CRCs, nothing we can do about it */ if (status == SPD_STATUS_OK || status == SPD_STATUS_CRC_ERROR) { diff --git a/tests/lib/dimm_info_util-test.c b/tests/lib/dimm_info_util-test.c index 3d11416..c83093b 100644 --- a/tests/lib/dimm_info_util-test.c +++ b/tests/lib/dimm_info_util-test.c @@ -2,6 +2,7 @@
#include <device/dram/ddr2.h> #include <device/dram/ddr3.h> +#include <device/dram/ddr4.h> #include <device/dram/ddr5.h> #include <dimm_info_util.h> #include <spd.h> @@ -157,9 +158,9 @@ }, { .memory_type = MEMORY_TYPE_DDR4, - .udimm_allowed = {DDR4_SPD_UDIMM, DDR4_SPD_MINI_UDIMM}, - .rdimm_allowed = {DDR4_SPD_RDIMM, DDR4_SPD_MINI_RDIMM}, - .expected_module_type = DDR4_SPD_SODIMM, + .udimm_allowed = {SPD_DDR4_DIMM_TYPE_UDIMM, SPD_DDR4_DIMM_TYPE_MINI_UDIMM}, + .rdimm_allowed = {SPD_DDR4_DIMM_TYPE_RDIMM, SPD_DDR4_DIMM_TYPE_MINI_RDIMM}, + .expected_module_type = SPD_DDR4_DIMM_TYPE_SO_DIMM, }, {.memory_type = MEMORY_TYPE_DDR5, .udimm_allowed = {DDR5_SPD_UDIMM, DDR5_SPD_MINI_UDIMM},
-
Elyes Haouas (Code Review)