[M] Change in coreboot[main]: [WIP,UNTESTED]Add 64bit support to Intel Alderlake

[Arthur Heymans (Code Review)]

Attention is currently required from: Andrey Petrov, Angel Pons, Jérémy Compostella, Nick Vaccaro, Ronak Kanabar, Subrata Banik.

Hello Andrey Petrov, Angel Pons, Jérémy Compostella, Nick Vaccaro, Ronak Kanabar, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/79823?usp=email

to look at the new patch set (#2).

Change subject: [WIP,UNTESTED]Add 64bit support to Intel Alderlake
......................................................................

[WIP,UNTESTED]Add 64bit support to Intel Alderlake

With FSP being 32bit and expecting 32bit PPI we need some 32/64bit dance
to hook up coreboot MP services.

Signed-off-by: Arthur Heymans 
Change-Id: Ib5cce9503b5b12d6f0d9b44720ac94006ed16602
---
M src/cpu/x86/64bit/mode_switch2.S
M src/cpu/x86/64bit/prot2long.inc
M src/drivers/intel/fsp2_0/Makefile.inc
A src/drivers/intel/fsp2_0/fsp_debug_event_as.S
M src/drivers/intel/fsp2_0/ppi/Makefile.inc
A src/drivers/intel/fsp2_0/ppi/mp_service1_as.S
M src/drivers/intel/fsp2_0/ppi/mp_service2.c
A src/drivers/intel/fsp2_0/ppi/mp_service2_as.S
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/romstage/fsp_params.c
13 files changed, 192 insertions(+), 27 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/79823/2