Change in coreboot[master]: psp_verstage: add new svc for cezanne

[Rob Barnes (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won, Felix Held.
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61368 )

Change subject: psp_verstage: add new svc for cezanne
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Patch Set 1:

(2 comments)

File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h:

https://review.coreboot.org/c/coreboot/+/61368/comment/1e00c1df_e4465518 
PS1, Line 53: #define SVC_SET_PLATFORM_BOOT_MODE          0x6C
nit: Why is 0x6B skipped?

https://review.coreboot.org/c/coreboot/+/61368/comment/26c08f33_9dc6059b 
PS1, Line 144:     CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT     = 0x4, // used for boundary check
nit: I think CROS is more commonly used than CHROME_BOOK