[XS] Change in coreboot[main]: mb/google/brya/vell: Enable RTD3 for SSD to resolve S0ix issue

[Pranava Y N (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Subrata Banik.

Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86646?usp=email

to look at the new patch set (#2).

Change subject: mb/google/brya/vell: Enable RTD3 for SSD to resolve S0ix issue
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mb/google/brya/vell: Enable RTD3 for SSD to resolve S0ix issue

Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on vell and verify that the device
suspends to S0ix.

Change-Id: I9015f992cc797af013e8882630220b3df41dc9b3
Signed-off-by: Pranava Y N 
---
M src/mainboard/google/brya/variants/vell/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/86646/2