[S] Change in coreboot[main]: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING

[Gareth Yu (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Gareth Yu, Jayvik Desai, Kapil Porwal, Lawrence Chang, Nick Vaccaro, Paul Menzel, SH Kim, Simon Yang, Subrata Banik.

Gareth Yu has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/86838?usp=email )

Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
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Patch Set 18:

(1 comment)

File src/mainboard/google/brya/variants/meliks/ramstage.c:

https://review.coreboot.org/c/coreboot/+/86838/comment/859ebf33_3ea5fe76?usp... :
PS17, Line 20: 0xf
> > Unfortunately, ```mainboard_silicon_init_params``` is too early to use igd bar. […]

Yes, hardcoding the MMIO address is possible. The reason is we need to clear the same system memory which is used by GFX before warm boot. However, I have found 2 possible addresses are used for TWL, 0x81000000 or 0xAF000000.  It means that the address can be changed according to different PCI devices. Even only for this project, I can't say the PCI devices are consistent until its EOL. Thought?