[M] Change in coreboot[main]: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING

[Gareth Yu (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Gareth Yu, Jayvik Desai, Kapil Porwal, Lawrence Chang, Nick Vaccaro, Paul Menzel, SH Kim, Simon Yang, Subrata Banik.

Gareth Yu has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/86838?usp=email )

Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
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Patch Set 23:

(2 comments)

File src/mainboard/google/brya/variants/meliks/ramstage.c:

https://review.coreboot.org/c/coreboot/+/86838/comment/34b0bf25_7d8d98be?usp... :
PS19, Line 36: 	if (!igd_base)
> `that open brace { should be on the previous line`

Please fix.

File src/mainboard/google/brya/variants/meliks/ramstage.c:

https://review.coreboot.org/c/coreboot/+/86838/comment/ff47c9a9_de66c424?usp... :
PS21, Line 55: 	   the function consistent relies on software forcing the DPHY CLK timing to
> `trailing whitespace`

Please fix.