[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage

[Yidi Lin (Code Review)]

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86013?usp=email )

(

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage
......................................................................

soc/mediatek/mt8196: Add mtk-fsp loader in ramstage

MediaTek firmware support package (mtk-fsp) contains romstage and
ramstage blobs. Add support for the ramstage blob, which includes:
- UFS mphy settings.
- DPAC (Device Access Permission Control) settings.
- MMinfra (Multimedia Infrastrucutre) settings.
- SMPU (Security Memory Protection Unit) settings.
- Advanced CPU frequency control.

BUG=b:373797027
TEST=build pass, boot ok.
Load and run mtk_fsp with following logs:
[INFO ] CBFS: Found 'fallback/mtk_fsp_ramstage' @0xfca00 size 0x263d in
        mcache @0xfffdd5a0
[DEBUG] read SPI 0x4fea88 0x263d: 773 us, 12663 KB/s, 101.304 Mbps
[INFO ] VB2:vb2_digest_init() 9789 bytes, hash algo 2, HW acceleration
        enabled
[INFO ] _start: MediaTek FSP_RAMSTAGE interface version: 1.0
[INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_ramstage at phase
        0x50 done

Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21
Signed-off-by: Jarried Lin 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86013
Reviewed-by: Yu-Ping Wu 
Reviewed-by: Yidi Lin 
Tested-by: build bot (Jenkins) 
---
M src/soc/mediatek/common/include/soc/memlayout.h
M src/soc/mediatek/common/include/soc/mtk_fsp_common.h
M src/soc/mediatek/mt8196/Makefile.mk
M src/soc/mediatek/mt8196/include/soc/memlayout.ld
M src/soc/mediatek/mt8196/soc.c
5 files changed, 20 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved
  Yidi Lin: Looks good to me, approved

diff --git a/src/soc/mediatek/common/include/soc/memlayout.h b/src/soc/mediatek/common/include/soc/memlayout.h
index f51c2a1..9e5f11b 100644
--- a/src/soc/mediatek/common/include/soc/memlayout.h
+++ b/src/soc/mediatek/common/include/soc/memlayout.h
@@ -18,5 +18,8 @@
    _ = ASSERT(size % 4K == 0, \
    	"DRAM DMA buffer should be multiple of smallest page size (4K)!");

+#define FSP_RAMSTAGE_INIT_CODE(addr, size) \
+	REGION(fsp_ramstage_init_code, addr, size, 64K)
+
 #define EARLY_INIT(addr, size) \
    REGION(early_init_data, addr, size, 4)
diff --git a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h
index ea3d46f..99453ba 100644
--- a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h
+++ b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h
@@ -33,6 +33,7 @@
    FSP_PARAM_TYPE_INVALID = 0,
    /* 0x40000000+ reserved for input type params */
    FSP_PARAM_TYPE_IN = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_IN),
+	FSP_PARAM_TYPE_STORAGE,

/* 0x80000000+ reserved for output type params */
    FSP_PARAM_TYPE_OUT = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_OUT),
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 073f67e..84bf3b6 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -97,6 +97,14 @@
 $(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
 cbfs-files-y += $(DRAM_CBFS)

+FSP_RAMSTAGE_CBFS := $(CONFIG_CBFS_PREFIX)/mtk_fsp_ramstage
+$(FSP_RAMSTAGE_CBFS)-file := $(MT8196_BLOB_DIR)/mtk_fsp_ramstage.elf
+$(FSP_RAMSTAGE_CBFS)-type := stage
+$(FSP_RAMSTAGE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+ifneq ($(wildcard $($(FSP_RAMSTAGE_CBFS)-file)),)
+cbfs-files-y += $(FSP_RAMSTAGE_CBFS)
+endif
+
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
    ./util/mtkheader/gen-bl-img.py mt8196 sf $< $@

diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
index f8ee114..6c35a47 100644
--- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
@@ -64,6 +64,7 @@
    POSTRAM_CBFS_CACHE(0x80100000, 2M)
    RAMSTAGE(0x80300000, 2M)
    OPTEE_BUF(0x80500000, 70M)
+	FSP_RAMSTAGE_INIT_CODE(0x90000000, 2M)

BL31(0x94600000, 0x200000)

diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index 1f1da7c..1636f29 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -8,8 +8,10 @@
 #include <soc/gpueb.h>
 #include <soc/mcupm.h>
 #include <soc/mmu_operations.h>
+#include <soc/mtk_fsp.h>
 #include <soc/pcie.h>
 #include <soc/sspm.h>
+#include <soc/storage.h>
 #include <soc/symbols.h>
 #include <symbols.h>

@@ -33,6 +35,11 @@

static void soc_init(struct device *dev)
 {
+	mtk_fsp_init(RAMSTAGE_SOC_INIT);
+	uint32_t storage_type = mainboard_get_storage_type();
+	mtk_fsp_add_param(FSP_PARAM_TYPE_STORAGE, sizeof(storage_type), &storage_type);
+	mtk_fsp_load_and_run();
+
    mtk_mmu_disable_l2c_sram();
    sspm_init();
    gpueb_init();