[S] Change in coreboot[main]: soc/intel/xeon_sp: Allow OS to control LTR and AER

[Patrick Rudolph (Code Review)]

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85561?usp=email )

Change subject: soc/intel/xeon_sp: Allow OS to control LTR and AER
......................................................................

soc/intel/xeon_sp: Allow OS to control LTR and AER

There's no reason to tell the OS to disable LTR. On UEFI and
on coreboot's GNR LTR is allowed, thus allow it for all Xeon-SP.

There's no SMM (RAS) code that is able to parse AER structures,
thus let the OS always control AER. On coreboot's GNR AER is
also always granted to the OS.

TEST: Run code on ocp/tiogapass and observed dmesg:
      The OS now prints:
acpi PNP0A08:04: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability LTR]

Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85561
Reviewed-by: Shuo Liu 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
Reviewed-by: Marvin Drees 
---
M src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
3 files changed, 9 insertions(+), 3 deletions(-)

Approvals:
  Angel Pons: Looks good to me, approved
  build bot (Jenkins): Verified
  Shuo Liu: Looks good to me, approved
  Marvin Drees: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
index ffe692d..0095aa5 100644
--- a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
+++ b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
@@ -32,8 +32,10 @@
    	Method (_OSC, 4, NotSerialized)				\
    	{							\
    		Return (_SB.POSC(Arg0, Arg1, Arg2, Arg3,	\
-				(PCIE_CAP_STRUCTURE_CONTROL|		\
+				(PCIE_LTR_CONTROL|			\
+				PCIE_CAP_STRUCTURE_CONTROL|		\
    			PCIE_PME_CONTROL|			\
+				PCIE_AER_CONTROL|			\
    			PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0))	\
    	}							\
    }
diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
index bf02766..3ff3635 100644
--- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
+++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
@@ -39,8 +39,10 @@
    Method (_OSC, 4, NotSerialized)
    {
    	Return (_SB.POSC(Arg0, Arg1, Arg2, Arg3,
-			(PCIE_CAP_STRUCTURE_CONTROL|
+			(PCIE_LTR_CONTROL|
+			PCIE_CAP_STRUCTURE_CONTROL|
    		PCIE_PME_CONTROL|
+			PCIE_AER_CONTROL|
    		PCIE_NATIVE_HOTPLUG_CONTROL), 1,
    		CXL_ERROR_REPORTING_CONTROL))
    }
diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
index a81f28a..83a6efa 100644
--- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
+++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
@@ -37,8 +37,10 @@
    Method (_OSC, 4, NotSerialized)
    {
    	Return (_SB.POSC(Arg0, Arg1, Arg2, Arg3,
-			(PCIE_CAP_STRUCTURE_CONTROL|
+			(PCIE_LTR_CONTROL|
+			PCIE_CAP_STRUCTURE_CONTROL|
    		PCIE_PME_CONTROL|
+			PCIE_AER_CONTROL|
    		PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0))
    }
 }