Attention is currently required from: Tarun Tuli, Sean Rhodes, Subrata Banik, Kapil Porwal, Lean Sheng Tan, Werner Zeh.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70052 )
Change subject: soc/intel: Improve TCO accessors ......................................................................
soc/intel: Improve TCO accessors
Renames tco_read_reg() to tco_read16(). Renames tco_write_reg() to tco_write16().
Implement bitwise operations using <arch/io_bitops.h>.
Change-Id: I0090585bf6f30482952af40a985b086cf7bd91e6 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/elkhartlake/bootblock/bootblock.c M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/pmutil.c 12 files changed, 75 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/70052/1
diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 300ac71..80391ac 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -229,8 +229,8 @@ { uint8_t *pmc;
- ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS);
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 1f641de..5c6622c 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -154,8 +154,8 @@ { uintptr_t pmc_bar0 = soc_read_pmc_base();
- ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS);
ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 2219f65..6f471ec 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -222,8 +222,8 @@ { uint8_t *pmc;
- ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS);
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
diff --git a/src/soc/intel/common/block/include/intelblocks/tco.h b/src/soc/intel/common/block/include/intelblocks/tco.h index 35cbfb1..2012818 100644 --- a/src/soc/intel/common/block/include/intelblocks/tco.h +++ b/src/soc/intel/common/block/include/intelblocks/tco.h @@ -17,7 +17,7 @@ * and returns the status bits set. */ uint32_t tco_reset_status(void); -uint16_t tco_read_reg(uint16_t tco_reg); -void tco_write_reg(uint16_t tco_reg, uint16_t value); +uint16_t tco_read16(uint16_t tco_reg); +void tco_write16(uint16_t tco_reg, uint16_t value);
#endif /* SOC_INTEL_COMMON_BLOCK_TCO_H */ diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 12b176c..f678a53 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -29,36 +29,45 @@ return TCO_BASE_ADDRESS; }
-uint16_t tco_read_reg(uint16_t tco_reg) +uint16_t tco_read16(uint16_t tco_reg) { - uint16_t tcobase; - - tcobase = tco_get_bar(); - - return inw(tcobase + tco_reg); + return io_read16(tco_get_bar() + tco_reg); }
-void tco_write_reg(uint16_t tco_reg, uint16_t value) +void tco_write16(uint16_t tco_reg, uint16_t value) { - uint16_t tcobase; + io_write16(tco_get_bar() + tco_reg, value); +}
- tcobase = tco_get_bar(); +uint16_t tco_rwc16(uint16_t tco_reg) +{ + return io_rwc16(tco_get_bar() + tco_reg); +}
- outw(value, tcobase + tco_reg); +void tco_setbits16(uint16_t tco_reg, uint16_t mask) +{ + io_setbits16(tco_get_bar() + tco_reg, mask); +} + +void tco_clrbits16(uint16_t tco_reg, uint16_t mask) +{ + io_clrbits16(tco_get_bar() + tco_reg, mask); +} + +void tco_clrsetbits16(uint16_t tco_reg, uint16_t clr, uint16_t set) +{ + io_clrsetbits16(tco_get_bar() + tco_reg, clr, set); }
void tco_lockdown(void) { - uint16_t tcocnt; const pci_devfn_t dev = PCH_DEV_SMBUS;
/* TCO base address lockdown */ pci_or_config32(dev, TCOCTL, TCO_BASE_LOCK);
/* TCO Lock down */ - tcocnt = tco_read_reg(TCO1_CNT); - tcocnt |= TCO_LOCK; - tco_write_reg(TCO1_CNT, tcocnt); + tco_setbits16(TCO1_CNT, TCO_LOCK); }
uint32_t tco_reset_status(void) @@ -67,12 +76,12 @@ uint16_t tco2_sts;
/* TCO Status 1 register */ - tco1_sts = tco_read_reg(TCO1_STS); - tco_write_reg(TCO1_STS, tco1_sts); + tco1_sts = tco_rwc16(TCO1_STS);
+ /* First clear only TCO_STS_SECOND_TO here ?? */ /* TCO Status 2 register */ - tco2_sts = tco_read_reg(TCO2_STS); - tco_write_reg(TCO2_STS, tco2_sts | TCO2_STS_SECOND_TO); + tco2_sts = tco_read16(TCO2_STS); + tco_write16(TCO2_STS, tco2_sts | TCO2_STS_SECOND_TO);
return (tco2_sts << 16) | tco1_sts; } @@ -80,24 +89,23 @@ /* Stop TCO timer */ static void tco_timer_disable(void) { - uint16_t tcocnt; + tco_setbits16(TCO1_CNT, TCO_TMR_HLT); +}
- /* Program TCO timer halt */ - tcocnt = tco_read_reg(TCO1_CNT); - tcocnt |= TCO_TMR_HLT; - tco_write_reg(TCO1_CNT, tcocnt); +/* NO_REBOOT is enabled via bit 0 in TCO1_CNT. */ +#define TCO_NO_REBOOT (1 << 0) + +void tco_set_no_reboot(void) +{ + printk(BIOS_DEBUG, "TCO: Disable reset on second expiration.\n"); + tco_setbits16(TCO1_CNT, TCO_NO_REBOOT); }
/* Enable and initialize TCO intruder SMI */ static void tco_intruder_smi_enable(void) { - uint16_t tcocnt; - /* Make TCO issue an SMI on INTRD_DET assertion */ - tcocnt = tco_read_reg(TCO2_CNT); - tcocnt &= ~TCO_INTRD_SEL_MASK; - tcocnt |= TCO_INTRD_SEL_SMI; - tco_write_reg(TCO2_CNT, tcocnt); + tco_clrsetbits16(TCO2_CNT, TCO_INTRD_SEL_MASK, TCO_INTRD_SEL_SMI); }
/* Enable TCO BAR using SMBUS TCO base to access TCO related register */ diff --git a/src/soc/intel/elkhartlake/bootblock/bootblock.c b/src/soc/intel/elkhartlake/bootblock/bootblock.c index cc0bb8f..f96e678 100644 --- a/src/soc/intel/elkhartlake/bootblock/bootblock.c +++ b/src/soc/intel/elkhartlake/bootblock/bootblock.c @@ -32,11 +32,7 @@
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); - if (CONFIG(SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN)) { - uint16_t reg = tco_read_reg(TCO1_CNT); - /* NO_REBOOT is enabled via bit 0 in TCO1_CNT. */ - reg |= 0x01; - tco_write_reg(TCO1_CNT, reg); - printk(BIOS_DEBUG, "TCO: Disable reset on second expiration.\n"); - } + + if (CONFIG(SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN)) + tco_set_no_reboot(); } diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 7dee348..bb14070 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -238,8 +238,8 @@ { uint8_t *pmc;
- ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS);
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index f1d4d21..0f5acdd 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -238,8 +238,8 @@ { uint8_t *pmc;
- ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS);
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index 7e00ca5..34e0f32 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -238,8 +238,8 @@ { uint8_t *pmc;
- ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS);
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 29ef32f..29b9df9 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -220,8 +220,8 @@ { uint8_t *pmc;
- ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS);
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index c234e30..5e97c97 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -224,8 +224,8 @@ { uint8_t *pmc;
- ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS);
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 1fb2b07..a308020 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -244,8 +244,8 @@ { uint8_t *pmc;
- ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS);
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
-
Kyösti Mälkki (Code Review)