Change in coreboot[master]: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT

[Michał Żygowski (Code Review)]

Attention is currently required from: Angel Pons, Patrick Rudolph.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59523 )

Change subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT
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Patch Set 6:

(4 comments)

File src/northbridge/intel/sandybridge/romstage.c:

https://review.coreboot.org/c/coreboot/+/59523/comment/8d25c3b6_2885c901 
PS2, Line 78: #if CONFIG(INTEL_TXT)
> > I'm afraid I don't follow. The only redundant MSR writing I see is the one CB:59521 adds. […]

Done

File src/northbridge/intel/sandybridge/romstage.c:

https://review.coreboot.org/c/coreboot/+/59523/comment/0a5356e3_5a9f380a 
PS3, Line 28: #if CONFIG(INTEL_TXT)
> Actually not, we can always configure the DPR

Done

https://review.coreboot.org/c/coreboot/+/59523/comment/e0869818_45c524c9 
PS3, Line 35: /* 3 MiB should be enough */
> I'd omit this comment.

Done

https://review.coreboot.org/c/coreboot/+/59523/comment/cf0e86c1_20384e67 
PS3, Line 36: 	pci_write_config32(HOST_BRIDGE, DPR, dpr.raw);
> dpr. […]

Added a comment to explain how it works inside the configure_dpr function.