Attention is currently required from: Nico Huber, Patrick Rudolph. Hello Nico Huber,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/49890
to review the following change.
Change subject: nb/intel/sandybridge: Correct raminit stepping checks ......................................................................
nb/intel/sandybridge: Correct raminit stepping checks
Untested.
Change-Id: I1674834dfb72d8f95ba666fcc43348c5bc85462e Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/model_206ax/model_206ax.h M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_native.c 3 files changed, 6 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/49890/1
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 04e4639..72e1eb3 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -22,17 +22,8 @@ #define IVB_STEP_E0 8 #define IVB_STEP_E1 9
-#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) -#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) -#define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5) -#define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6) -#define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7) - -#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) -#define IS_IVY_CPU_C(x) ((x & 0xf) == 4) -#define IS_IVY_CPU_K(x) ((x & 0xf) == 5) -#define IS_IVY_CPU_D(x) ((x & 0xf) == 6) -#define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) +#define IS_SANDY_CPU(x) (((x) & 0xffff0) == 0x206a0) +#define IS_IVY_CPU(x) (((x) & 0xffff0) == 0x306a0)
/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 85ba943..6972425 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -127,7 +127,7 @@ * ODT stretch: * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. */ - if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) { + if (IS_SANDY_CPU(ctrl->cpu) && (ctrl->cpu & 0xf) == SNB_STEP_C0) { if (stretch == 2) stretch = 3;
@@ -2435,7 +2435,7 @@ }
/* Only enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization on later steppings */ - const bool enable_iosav_opt = IS_IVY_CPU_D(ctrl->cpu) || IS_IVY_CPU_E(ctrl->cpu); + const bool enable_iosav_opt = (ctrl->cpu & 0xf) >= IVB_STEP_D0;
if (enable_iosav_opt) MCHBAR32(MCMNTS_SPARE) = 1; @@ -2731,7 +2731,7 @@
void set_wmm_behavior(const u32 cpu) { - if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { + if (IS_SANDY_CPU(cpu) && (cpu & 0xf) < SNB_STEP_C0) { MCHBAR32(SC_WDBWM) = 0x141d1519; } else { MCHBAR32(SC_WDBWM) = 0x551d1519; diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9961e89..9bdbdfd 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -184,7 +184,7 @@ .raw = MCHBAR32(CRCOMPOFST1_ch(channel)), };
- if (IS_SANDY_CPU(ctrl->cpu) && !IS_SANDY_CPU_D2(ctrl->cpu)) { + if (IS_SANDY_CPU(ctrl->cpu) && (ctrl->cpu & 0xf) != SNB_STEP_D2) { union comp_ofst_1_reg comp_ofst_1 = orig_comp;
comp_ofst_1.clk_odt_up = 1;