Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48528
to review the following change.
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 343 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index be45de4..885afb3 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -98,4 +98,74 @@ int default 64
+menu "PSP Configuration Options" + +config AMDFW_OUTSIDE_CBFS + bool + default n + help + The AMDFW (PSP) is typically locatable in cbfs. Select this + option to manually attach the generated amdfw.rom outside of + cbfs. The location is selected by the FWM position. + +config AMD_FWM_POSITION_INDEX + int "Firmware Directory Table location (0 to 5)" + range 0 5 + default 0 if BOARD_ROMSIZE_KB_512 + default 1 if BOARD_ROMSIZE_KB_1024 + default 2 if BOARD_ROMSIZE_KB_2048 + default 3 if BOARD_ROMSIZE_KB_4096 + default 4 if BOARD_ROMSIZE_KB_8192 + default 5 if BOARD_ROMSIZE_KB_16384 + help + Typically this is calculated by the ROM size, but there may + be situations where you want to put the firmware directory + table in a different location. + 0: 512 KB - 0xFFFA0000 + 1: 1 MB - 0xFFF20000 + 2: 2 MB - 0xFFE20000 + 3: 4 MB - 0xFFC20000 + 4: 8 MB - 0xFF820000 + 5: 16 MB - 0xFF020000 + +comment "AMD Firmware Directory Table set to location for 512KB ROM" + depends on AMD_FWM_POSITION_INDEX = 0 +comment "AMD Firmware Directory Table set to location for 1MB ROM" + depends on AMD_FWM_POSITION_INDEX = 1 +comment "AMD Firmware Directory Table set to location for 2MB ROM" + depends on AMD_FWM_POSITION_INDEX = 2 +comment "AMD Firmware Directory Table set to location for 4MB ROM" + depends on AMD_FWM_POSITION_INDEX = 3 +comment "AMD Firmware Directory Table set to location for 8MB ROM" + depends on AMD_FWM_POSITION_INDEX = 4 +comment "AMD Firmware Directory Table set to location for 16MB ROM" + depends on AMD_FWM_POSITION_INDEX = 5 + +config AMDFW_CONFIG_FILE + string + default "src/soc/amd/cezanne/fw.cfg" + +config USE_PSPSECUREOS + bool + default y + help + Include the PspSecureOs and PspTrustlet binaries in the PSP build. + + If unsure, answer 'y' + +config PSP_LOAD_MP2_FW + bool + default n + help + Include the MP2 firmwares and configuration into the PSP build. + + If unsure, answer 'n' + +config PSP_LOAD_S0I3_FW + bool + default n + help + +endmenu + endif # SOC_AMD_CEZANNE diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 946e480..d68f080 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -13,4 +13,196 @@
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
+MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) + +# ROMSIG Normally At ROMBASE + 0x20000 +# Overridden by CONFIG_AMD_FWM_POSITION_INDEX +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA | | | | +# +-----------+---------------+----------------+------------+ +# | | PSPDIR ADDR | BIOSDIR ADDR | +# +-----------+---------------+----------------+ + +CEZANNE_FWM_POSITION=$(call int-add, \ + $(call int-subtract, 0xffffffff \ + $(call int-shift-left, \ + 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + +#ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +#endif + +ifeq ($(CONFIG_USE_PSPSECUREOS),y) +# types = 0x2 +OPT_PSP_USE_PSPSECUREOS="--use-pspsecureos" endif + + +#ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +#else +# Disable MP2 firmware loading +#PSP_SOFTFUSE_BITS += 29 +#endif + +#ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) +OPT_PSP_LOAD_S0I3_FW="--load-s0i3" +#endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') +# type = 0x63 - construct APOB NV base/size from flash map +# The flashmap section used for this is expected to be named RW_MRC_CACHE +APOB_NV_SIZE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_SIZE" $(obj)/fmap_config.h | awk '{print $$(NF)}') +APOB_NV_BASE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_START" $(obj)/fmap_config.h | awk '{print $$(NF)}') + +# type = 0x66 +PSP_UCODE_FILE1=$(FIRMWARE_LOCATION)/UcodePatch_PCO_B1.bin +PSP_UCODE_FILE2=$(FIRMWARE_LOCATION)/UcodePatch_PCO_B0.bin +PSP_UCODE_FILE3=$(FIRMWARE_LOCATION)/UcodePatch_RV2_A0.bin + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +_PSP_SHAREDMEM_BASE=$(shell grep _psp_sharedmem_dram $(obj)/cbfs/$(CONFIG_CBFS_PREFIX)/bootblock.map | cut -f1 -d' ') +PSP_SHAREDMEM_BASE=$(shell printf "0x%s" $(_PSP_SHAREDMEM_BASE)) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) +endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK + +# type = 0xb - See #55758 (NDA) for bit definitions. +PSP_SOFTFUSE_BITS += 28 + +#hardcode post code to eSPI +PSP_SOFTFUSE_BITS += 15 6 + +# Helper function to return a value with given bit set +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) + +#OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ +# $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ +# --instance $(shell printf "%x" $$(($(i)-1))) --apcb )) +#OPT_PSP_APCB_FILES= --instance 0 --apcb $(APCB_SOURCES) --instance 10 --apcb $(APCB_SOURCES_RECOVERY) --instance 18 --apcb $(APCB_SOURCES_68) +OPT_PSP_APCB_FILES= --instance 0 --apcb $(APCB_SOURCES) --instance 10 --apcb $(APCB_SOURCES_RECOVERY) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) +OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) +OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +#ifeq ($(CONFIG_VBOOT),) +#OPT_APOB0_NV_SIZE=$(OPT_APOB_NV_SIZE) +#OPT_APOB0_NV_BASE=$(OPT_APOB_NV_BASE) +#endif + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + +# Add all the files listed in the config file +POUND_SIGN=$(call strip_quotes, "#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_USE_PSPSECUREOS) \ + $(OPT_PSP_LOAD_MP2_FW) \ + $(OPT_PSP_LOAD_S0I3_FW) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SEC_DEBUG_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + --combo-capable \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --soc-name "Cezanne" \ + --flashsize $(CONFIG_ROM_SIZE) + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(PSP_VERSTAGE_FILE) \ + $(PSP_VERSTAGE_SIG_FILE) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(OPT_PSPBTLDR_FILE) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB0_NV_SIZE) \ + $(OPT_APOB0_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + --location $(shell printf "%#x" $(CEZANNE_FWM_POSITION)) \ + --multilevel \ + --output $@ + +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(CEZANNE_FWM_POSITION) +apu/amdfw-type := raw + +endif # ($(CONFIG_SOC_AMD_CEZANNE),y) diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg new file mode 100644 index 0000000..a482e8c --- /dev/null +++ b/src/soc/amd/cezanne/fw.cfg @@ -0,0 +1,81 @@ +# PSP fw config file + +FIRMWARE_LOCATION 3rdparty/amd_blobs/cezanne/PSP + +# type file +AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn +PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin +PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin +#3 +PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin +#4? +PSPNVRAM_FILE PspNvramCZN_2.bin + +PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin +PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_CZN.stkn +#B? +PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin +PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin +PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin +PSP_HW_IPCFG_FILE TypeId0x20_HwIpCfg_CZN_A0.sbin +PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin +#0x22 is not needed? +#AMD_TOKEN_UNLOCK_FILE TypeId0x22_SecureEmptyToken.bin +#0x24? +PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin +PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin +#PSP_MP2FW0_WALLE_FILE +PSP_MP2FW1_FILE TypeId0x125_MP2WALLE_CZN.sbin +#0x28 +AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin +#0x29 size=0, useless? +PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin +#0x2D +PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_CZN.sbin +#0x30 +PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin +#0x3C +VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_CZN.sbin +#0x45 +SECURE_POLICY_L1_FILE TypeId0x45_SecurePolicyL1_CZN.sbin +#0x44 +UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin +#0x47 +DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin +#0x50 +KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin +#0x51 +KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin +#0x58 +DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin +#0x59 +DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin +#0x54 +RPMC_FILE PspNvramCZN_4.bin + +## BDT +#0x60 +#APCB_CZN_D4_Updatable.bin +#0x68 +#APCB_CZN_D4_DefaultRecovery.bin +#0x68 +#APCB_CZN_D4_Updatable_68.bin +#0x61 +#0x62 +#0x63 +#APOB_NV_FILE APOB_NV_RV.bin + +#0x64 +PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin +#0x65 +PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin +#0x64 +PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin +#0x65 +PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin + +#0x66 #in other place +#UcodePatch_CZN_A0.bin + +#0x6A +PSP_MP2CFG_FILE MP2FWConfig.sbin
Hello build bot (Jenkins), Jason Glenesk, Patrick Georgi, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48528
to look at the new patch set (#2).
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 344 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/2
Marshall Dawson has uploaded a new patch set (#5) to the change originally created by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 344 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/5
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48528/6/src/soc/amd/cezanne/fw.cfg File src/soc/amd/cezanne/fw.cfg:
https://review.coreboot.org/c/coreboot/+/48528/6/src/soc/amd/cezanne/fw.cfg@... PS6, Line 11: #4? : PSPNVRAM_FILE PspNvramCZN_2.bin I don't believe this should be an actual file. Although we used to include it for older devices, it's space the PSP uses for fTPM info AFAIK. And it's simply erased space in the flash. I confirmed it's all FFs in Majolica's image.
https://review.coreboot.org/c/coreboot/+/48528/6/src/soc/amd/cezanne/fw.cfg@... PS6, Line 28: PSP_MP2FW1_FILE TypeId0x125_MP2WALLE_CZN.sbin I don't know what this is. I'm not seeing a FW name that looks like it in the Cezanne PI. And 125 doesn't sound right because the type field is only 8 bits. In Majolica's UEFI image I only see a single MP2 FW file.
https://review.coreboot.org/c/coreboot/+/48528/6/src/soc/amd/cezanne/fw.cfg@... PS6, Line 54: PspNvramCZN_4.bin This isn't correct. However we should be reserving space for the RPMC and not passing a file in.
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 6:
Here are some Majolica APCB files you can use. CB:48683.
Hello build bot (Jenkins), Jason Glenesk, Patrick Georgi, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48528
to look at the new patch set (#7).
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 344 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/7
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 7:
(3 comments)
only did a very brief review and didn't look into the details yet
https://review.coreboot.org/c/coreboot/+/48528/7/src/soc/amd/cezanne/Kconfig File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/48528/7/src/soc/amd/cezanne/Kconfig... PS7, Line 104: config AMDFW_OUTSIDE_CBFS : bool : default n : help : The AMDFW (PSP) is typically locatable in cbfs. Select this : option to manually attach the generated amdfw.rom outside of : cbfs. The location is selected by the FWM position. this can be removed, since it's unused and was implemented in a very unsafe way when i removed it from picasso
https://review.coreboot.org/c/coreboot/+/48528/7/src/soc/amd/cezanne/Makefil... File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/7/src/soc/amd/cezanne/Makefil... PS7, Line 64: #PSP_SOFTFUSE_BITS += 29 this probably shouldn't be commented out
https://review.coreboot.org/c/coreboot/+/48528/7/src/soc/amd/cezanne/fw.cfg File src/soc/amd/cezanne/fw.cfg:
https://review.coreboot.org/c/coreboot/+/48528/7/src/soc/amd/cezanne/fw.cfg@... PS7, Line 11: #4? : #PSPNVRAM_FILE PspNvramCZN_2.bin please remove instead of commenting out
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 9:
(1 comment)
Could you please verify that amdfwtool fails immediately if the directory or files aren't present? I think there's an issue there that's causing builder problems.
https://review.coreboot.org/c/coreboot/+/48528/9/src/soc/amd/cezanne/fw.cfg File src/soc/amd/cezanne/fw.cfg:
https://review.coreboot.org/c/coreboot/+/48528/9/src/soc/amd/cezanne/fw.cfg@... PS9, Line 3: 3rdparty/amd_blobs/cezanne/PSP These files aren't checked into this directory yet, so the guybrush build will probably keep failing until they are.
It seems like the build isn't failing immediately on reaching this point though. It looks like it's filling the hdd on the builder and running for a long time before failing.
Hello build bot (Jenkins), Jason Glenesk, Martin Roth, Patrick Georgi, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48528
to look at the new patch set (#10).
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 344 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/10
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 12: Code-Review-1
Updating this patch causes the builders to get into a loop building guybrush. It will never pass the build as is. Please look into what's causing that and fix the issue before repushing.
Hello build bot (Jenkins), Jason Glenesk, Martin Roth, Patrick Georgi, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48528
to look at the new patch set (#13).
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 344 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/13
Attention is currently required from: Bao Zheng. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 13:
(1 comment)
File src/soc/amd/cezanne/fw.cfg:
https://review.coreboot.org/c/coreboot/+/48528/comment/6a662312_cfc5f390 PS12, Line 56: ## BDT : #0x60 : #APCB_CZN_D4_Updatable.bin : #0x68 : #APCB_CZN_D4_DefaultRecovery.bin : #0x68 : #APCB_CZN_D4_Updatable_68.bin : #0x61 : #0x62 : #0x63 : #APOB_NV_FILE APOB_NV_RV.bin those should be removed
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 13:
(1 comment)
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/comment/d8210d81_f6628b08 PS13, Line 138: OPT_PSP_APCB_FILES= --instance 0 --apcb $(APCB_SOURCES) --instance 10 --apcb $(APCB_SOURCES_RECOVERY) this and the code in amdfwtool possibly needs some change to support this properly. haven't looked too closely at this though
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 340 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/14
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 297 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/15
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 300 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/16
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 16: Code-Review-2
(1 comment)
Patchset:
PS16: I'm making it so that the coreboot builders will refuse to build this patch until you can prove to me that it won't kill them anymore.
I mentioned it in patchset 9, and it's still killing the builders. It took down ultron all day today.
Please fix this.
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 308 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/18
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 293 insertions(+), 0 deletions(-)
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/mainboard/amd/majolica/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 4 files changed, 299 insertions(+), 0 deletions(-)
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 21:
(1 comment)
Patchset:
PS21: I really don't know why the Jekkins is still unhappy.
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 21:
(2 comments)
Patchset:
PS21:
I really don't know why the Jekkins is still unhappy.
see https://qa.coreboot.org/job/coreboot-gerrit/159975/console
File src/mainboard/amd/majolica/Kconfig:
https://review.coreboot.org/c/coreboot/+/48528/comment/b01b01c6_cac32cee PS21, Line 21: config AMD_FWM_POSITION_INDEX this should be in the majolica-related patch. in order for things to work, the majolica patch needs to be before this one
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Removed Code-Review-2 by Martin Roth martinroth@google.com
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 21:
(1 comment)
Patchset:
PS21: We established resource limits for builds now, so this change won't fill up disk space with logs anymore, but will be killed at some point. Due to that, we also took out Martin's test for this change again.
The issue is that oldconfig ends up in an endless loop which is logged to disk. At some point, the disk is full, blocking other builds running on the same machine.
Run `util/abuild/abuild` locally (with no local changes, in particular not to blobs) to reproduce the issue.
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 21:
(1 comment)
Patchset:
PS21: Removed the jenkins block. It looks like the process isn't dying properly and is spewing into a logfile. This causes the drives to fill up because even after the file is removed, it's still using drive space until the process is killed. Pgeorgi added a fix which will kill any process that's run for more than an hour of cpu time. We believe that should take care of the issue.
If we could figure out why the process is staying open, that would be helpful, but at least the builders shouldn't die anymore.
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 294 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/25
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 293 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/27
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 255 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/28
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 28:
(7 comments)
File src/mainboard/amd/majolica/Kconfig:
https://review.coreboot.org/c/coreboot/+/48528/comment/fe8eef59_5d415fe2 PS21, Line 21: config AMD_FWM_POSITION_INDEX
this should be in the majolica-related patch. […]
Done
File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/48528/comment/365835a2_7479ed72 PS7, Line 104: config AMDFW_OUTSIDE_CBFS : bool : default n : help : The AMDFW (PSP) is typically locatable in cbfs. Select this : option to manually attach the generated amdfw.rom outside of : cbfs. The location is selected by the FWM position.
this can be removed, since it's unused and was implemented in a very unsafe way when i removed it fr […]
Done
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/comment/f402fb06_03859818 PS7, Line 64: #PSP_SOFTFUSE_BITS += 29
this probably shouldn't be commented out
Done
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/comment/aebc7a29_6f43b529 PS13, Line 138: OPT_PSP_APCB_FILES= --instance 0 --apcb $(APCB_SOURCES) --instance 10 --apcb $(APCB_SOURCES_RECOVERY)
this and the code in amdfwtool possibly needs some change to support this properly. […]
Done
File src/soc/amd/cezanne/fw.cfg:
https://review.coreboot.org/c/coreboot/+/48528/comment/671158d8_79c3ba68 PS7, Line 11: #4? : #PSPNVRAM_FILE PspNvramCZN_2.bin
please remove instead of commenting out
Done
File src/soc/amd/cezanne/fw.cfg:
https://review.coreboot.org/c/coreboot/+/48528/comment/15e9b8a7_5ff34e93 PS9, Line 3: 3rdparty/amd_blobs/cezanne/PSP
These files aren't checked into this directory yet, so the guybrush build will probably keep failing […]
Done
File src/soc/amd/cezanne/fw.cfg:
https://review.coreboot.org/c/coreboot/+/48528/comment/e0b2cef8_db7972ef PS12, Line 56: ## BDT : #0x60 : #APCB_CZN_D4_Updatable.bin : #0x68 : #APCB_CZN_D4_DefaultRecovery.bin : #0x68 : #APCB_CZN_D4_Updatable_68.bin : #0x61 : #0x62 : #0x63 : #APOB_NV_FILE APOB_NV_RV.bin
those should be removed
Done
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 247 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/29
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 28:
(3 comments)
File src/soc/amd/cezanne/fw.cfg:
https://review.coreboot.org/c/coreboot/+/48528/comment/a4e2735b_40be802f PS6, Line 11: #4? : PSPNVRAM_FILE PspNvramCZN_2.bin
I don't believe this should be an actual file. […]
Done
https://review.coreboot.org/c/coreboot/+/48528/comment/2316f393_0d57fa04 PS6, Line 28: PSP_MP2FW1_FILE TypeId0x125_MP2WALLE_CZN.sbin
I don't know what this is. I'm not seeing a FW name that looks like it in the Cezanne PI. […]
Done
https://review.coreboot.org/c/coreboot/+/48528/comment/66304a74_521f2c27 PS6, Line 54: PspNvramCZN_4.bin
This isn't correct. However we should be reserving space for the RPMC and not passing a file in.
Done. https://review.coreboot.org/c/coreboot/+/49015 This change is a new feature which allocates some space without a actua file.
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 29:
(6 comments)
File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/48528/comment/ccdce65b_fd5b3fc6 PS29, Line 163: config PSP_LOAD_MP2_FW not sure if PSP_LOAD_MP2_FW and PSP_LOAD_S0I3_FW should be default y. for PSP_UNLOCK_SECURE_DEBUG i agree that it should be default y for now and changed back when we're done with the platform bring-up. i'm ok with keeping it as it is right now and have another look at it later
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/comment/81a767f1_d075495d PS29, Line 46: CONFIG_AMD_FWM_POSITION_INDEX there should probably be a check to make sure that this isn't an empty string instead of the number and if it is empty throw an error. see https://docs.zephyrproject.org/1.14.0/guides/kconfig/index.html#redundant-de... on the default of int in Kconfig. same for picasso
https://review.coreboot.org/c/coreboot/+/48528/comment/a00647c7_2af1a61a PS29, Line 113: OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) the other apob related things aren't in here, so i wonder if this one should also be removed for now and added back when the apob support is added
https://review.coreboot.org/c/coreboot/+/48528/comment/cfe8a8aa_29518e5a PS29, Line 137: $(OPT_SEC_DEBUG_FILE) \ this variable doesn't exist, so should probably be removed. same for picasso
https://review.coreboot.org/c/coreboot/+/48528/comment/052e7d5c_73fa99d3 PS29, Line 154: $(OPT_PSPBTLDR_FILE) \ this variable seems to be undefined, so i guess it can be removed. same for picasso
https://review.coreboot.org/c/coreboot/+/48528/comment/51ea4369_73700767 PS29, Line 156: $(OPT_VERSTAGE_FILE) \ : $(OPT_VERSTAGE_SIG_FILE) \ no verstage support yet, i'd remove those for now
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 253 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/30
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 261 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/31
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 252 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/34
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 34:
(6 comments)
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/comment/3e04c548_cbb83cdd PS29, Line 46: CONFIG_AMD_FWM_POSITION_INDEX
there should probably be a check to make sure that this isn't an empty string instead of the number […]
option1: write as 0$(CONFIG_AMD_FWM_POSITION_INDEX) option2: Give CONFIG_AMD_FWM_POSITION_INDEX a default value. Pushed as option2. For PCO, we need to check if it affects many boards.
https://review.coreboot.org/c/coreboot/+/48528/comment/4d0e3f43_f919db15 PS29, Line 113: OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base)
the other apob related things aren't in here, so i wonder if this one should also be removed for now […]
Done. The amdfwtool requires this APOB base address need to be defined.
https://review.coreboot.org/c/coreboot/+/48528/comment/65c77929_7ec34dbe PS29, Line 137: $(OPT_SEC_DEBUG_FILE) \
this variable doesn't exist, so should probably be removed. […]
Done
https://review.coreboot.org/c/coreboot/+/48528/comment/d58bc22c_9693f0be PS29, Line 154: $(OPT_PSPBTLDR_FILE) \
this variable seems to be undefined, so i guess it can be removed. […]
Done
https://review.coreboot.org/c/coreboot/+/48528/comment/9849455e_14efb3a8 PS29, Line 156: $(OPT_VERSTAGE_FILE) \ : $(OPT_VERSTAGE_SIG_FILE) \
no verstage support yet, i'd remove those for now
Done
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/comment/ded225d2_8129414c PS34, Line 117: OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ : $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ : $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) : PICASO uses $(if) to extract strings. It can handle the empty one.
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 253 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/35
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 34:
(2 comments)
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/comment/6155af5f_00979310 PS29, Line 46: CONFIG_AMD_FWM_POSITION_INDEX
option1: write as 0$(CONFIG_AMD_FWM_POSITION_INDEX) […]
Done
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/comment/1d3ccc0e_edd1eb08 PS34, Line 117: OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ : $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ : $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) :
PICASO uses $(if) to extract strings. It can handle the empty one.
Done
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 35:
(3 comments)
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/comment/93c80be7_8b0028a2 PS29, Line 46: CONFIG_AMD_FWM_POSITION_INDEX
Done
https://review.coreboot.org/c/coreboot/+/49816 The change for Picasso
https://review.coreboot.org/c/coreboot/+/48528/comment/e4d0be6a_79580030 PS29, Line 137: $(OPT_SEC_DEBUG_FILE) \
Done
https://review.coreboot.org/c/coreboot/+/49815
https://review.coreboot.org/c/coreboot/+/48528/comment/3347f797_57575f79 PS29, Line 154: $(OPT_PSPBTLDR_FILE) \
Done
also https://review.coreboot.org/c/coreboot/+/49815
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 36:
(2 comments)
File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/48528/comment/bdf2742e_61fae35b PS36, Line 126: default 4 if i remember correctly, Kconfig picks the first visible default, so this will basically hard-code AMD_FWM_POSITION_INDEX to 4 unless the board explicitly specifies another AMD_FWM_POSITION_INDEX default, since the mainboard Kconfig is processed before the soc's Kconfig
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/comment/b5cf4e0a_aaaaf3a1 PS29, Line 46: CONFIG_AMD_FWM_POSITION_INDEX
i'd say that CONFIG_AMD_FWM_POSITION_INDEX being empty should be a build error, since that means that the board didn't select a valid flash size which will likely cause some other issues as well; for example CONFIG_ROM_SIZE is also a parameter to amdfwtool.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 253 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/37
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 254 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/38
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 38:
(1 comment)
File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/48528/comment/9dfe2424_6adeb1db PS36, Line 126: default 4
if i remember correctly, Kconfig picks the first visible default, so this will basically hard-code A […]
Done
Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 38: Code-Review+2
(2 comments)
Patchset:
PS38: just ran a test and it works :)
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48528/comment/e7aca52a_ea6f25a6 PS29, Line 46: CONFIG_AMD_FWM_POSITION_INDEX
i'd say that CONFIG_AMD_FWM_POSITION_INDEX being empty should be a build error, since that means tha […]
Done
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 38: Code-Review+2
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#39).
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 252 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/39
Attention is currently required from: Martin Roth. Hello build bot (Jenkins), Jason Glenesk, Martin Roth, Patrick Georgi, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#40).
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 252 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/40
Attention is currently required from: Martin Roth. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 40:
(1 comment)
Patchset:
PS40: Split throwing error to another patch. Need re+2.
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Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 252 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/41
Attention is currently required from: Bao Zheng, Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 41: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao fishbaozi@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48528 Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/fw.cfg 3 files changed, 252 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 83825cd..ecdba5e 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -118,4 +118,73 @@ default 0xfedc9000 if UART_FOR_CONSOLE = 0 default 0xfedca000 if UART_FOR_CONSOLE = 1
+menu "PSP Configuration Options" + +config AMD_FWM_POSITION_INDEX + int "Firmware Directory Table location (0 to 5)" + range 0 5 + default 0 if BOARD_ROMSIZE_KB_512 + default 1 if BOARD_ROMSIZE_KB_1024 + default 2 if BOARD_ROMSIZE_KB_2048 + default 3 if BOARD_ROMSIZE_KB_4096 + default 4 if BOARD_ROMSIZE_KB_8192 + default 5 if BOARD_ROMSIZE_KB_16384 + help + Typically this is calculated by the ROM size, but there may + be situations where you want to put the firmware directory + table in a different location. + 0: 512 KB - 0xFFFA0000 + 1: 1 MB - 0xFFF20000 + 2: 2 MB - 0xFFE20000 + 3: 4 MB - 0xFFC20000 + 4: 8 MB - 0xFF820000 + 5: 16 MB - 0xFF020000 + +comment "AMD Firmware Directory Table set to location for 512KB ROM" + depends on AMD_FWM_POSITION_INDEX = 0 +comment "AMD Firmware Directory Table set to location for 1MB ROM" + depends on AMD_FWM_POSITION_INDEX = 1 +comment "AMD Firmware Directory Table set to location for 2MB ROM" + depends on AMD_FWM_POSITION_INDEX = 2 +comment "AMD Firmware Directory Table set to location for 4MB ROM" + depends on AMD_FWM_POSITION_INDEX = 3 +comment "AMD Firmware Directory Table set to location for 8MB ROM" + depends on AMD_FWM_POSITION_INDEX = 4 +comment "AMD Firmware Directory Table set to location for 16MB ROM" + depends on AMD_FWM_POSITION_INDEX = 5 + +config AMDFW_CONFIG_FILE + string + default "src/soc/amd/cezanne/fw.cfg" + +config USE_PSPSECUREOS + bool + default y + help + Include the PspSecureOs and PspTrustlet binaries in the PSP build. + + If unsure, answer 'y' + +config PSP_LOAD_MP2_FW + bool + default n + help + Include the MP2 firmwares and configuration into the PSP build. + + If unsure, answer 'n' + +config PSP_LOAD_S0I3_FW + bool + default n + help + Select this item to include the S0i3 file into the PSP build. + +config PSP_UNLOCK_SECURE_DEBUG + bool "Unlock secure debug" + default y + help + Select this item to enable secure debug options in PSP. + +endmenu + endif # SOC_AMD_CEZANNE diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 9a4aa80..a00a9f5 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -31,4 +31,149 @@
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
+MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) + +# ROMSIG Normally At ROMBASE + 0x20000 +# Overridden by CONFIG_AMD_FWM_POSITION_INDEX +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA | | | | +# +-----------+---------------+----------------+------------+ +# | | PSPDIR ADDR | BIOSDIR ADDR | +# +-----------+---------------+----------------+ + +CEZANNE_FWM_POSITION=$(call int-add, \ + $(call int-subtract, 0xffffffff \ + $(call int-shift-left, \ + 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" endif + +ifeq ($(CONFIG_USE_PSPSECUREOS),y) +# types = 0x2 +OPT_PSP_USE_PSPSECUREOS="--use-pspsecureos" +endif + + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +else +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 +endif + +ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) +OPT_PSP_LOAD_S0I3_FW="--load-s0i3" +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_68) $(APCB_SOURCES_RECOVERY) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +# type = 0x66 + +# type = 0xb - See #55758 (NDA) for bit definitions. +PSP_SOFTFUSE_BITS += 28 + +#hardcode post code to eSPI +PSP_SOFTFUSE_BITS += 15 6 + +# Helper function to return a value with given bit set +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ + $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ + $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +# Add all the files listed in the config file +POUND_SIGN=$(call strip_quotes, "#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_USE_PSPSECUREOS) \ + $(OPT_PSP_LOAD_MP2_FW) \ + $(OPT_PSP_LOAD_S0I3_FW) \ + --combo-capable \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --soc-name "Cezanne" \ + --flashsize $(CONFIG_ROM_SIZE) + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + --location $(shell printf "%#x" $(CEZANNE_FWM_POSITION)) \ + --multilevel \ + --output $@ + +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(CEZANNE_FWM_POSITION) +apu/amdfw-type := raw + +endif # ($(CONFIG_SOC_AMD_CEZANNE),y) diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg new file mode 100644 index 0000000..189bc9d --- /dev/null +++ b/src/soc/amd/cezanne/fw.cfg @@ -0,0 +1,38 @@ +# PSP fw config file + +FIRMWARE_LOCATION 3rdparty/amd_blobs/cezanne/PSP + +# type file +# PSP +AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn +PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin +PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin +PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin +PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin +PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_CZN.stkn +PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin +PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin +PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin +PSP_HW_IPCFG_FILE TypeId0x20_HwIpCfg_CZN_A0.sbin +PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin +PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin +PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin +AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin +PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin +PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_CZN.sbin +PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin +VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_CZN.sbin +SECURE_POLICY_L1_FILE TypeId0x45_SecurePolicyL1_CZN.sbin +UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin +DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin +KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin +KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin +DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin +DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin + +# BDT +PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin +PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin +PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin +PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin +PSP_MP2CFG_FILE MP2FWConfig.sbin