Attention is currently required from: David Wu, Hou-hsun Lee, Zhuohao Lee. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59576 )
Change subject: mb/google/brya/var/brask: Set PL and PsysPL ......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/brya/variants/brask/ramstage.c:
https://review.coreboot.org/c/coreboot/+/59576/comment/316594ce_78f20a48 PS1, Line 18: { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 5000, 45000, 80000, 80000, 159000 },
Those PL2/PL4 values look like coming from baseline config. […]
According to the HW design, we will use performance config. From doc#626774, 482 28W SKU which maps to PCI_DEVICE_ID_INTEL_ADL_P_ID_5 also has a new PL4 value 90W, right? Thanks.
https://review.coreboot.org/c/coreboot/+/59576/comment/5ebca809_295c96f4 PS1, Line 23: { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135, 257 },
If the psys_pmax_power is not used at all, I think it's better to remove it to avoid confusion. […]
Yes. psys_pmax is calculated by psys_imax_ma * volts_mv. Removed psys_pmax from the structure.
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Alan Huang (Code Review)