Change in coreboot[master]: soc/mediatek: Add function to raise the CPU frequency of MT8192

[CK HU (Code Review)]

Hello Weiyi Lu,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/45401

to review the following change.

Change subject: soc/mediatek: Add function to raise the CPU frequency of MT8192
......................................................................

soc/mediatek: Add function to raise the CPU frequency of MT8192

Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq().
Implement mt_pll_raise_little_cpu_freq() in MT8192.

Signed-off-by: Weiyi Lu 
Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe
---
M src/mainboard/google/kukui/romstage.c
M src/mainboard/google/oak/romstage.c
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8173/pll.c
M src/soc/mediatek/mt8183/pll.c
M src/soc/mediatek/mt8192/include/soc/pll.h
M src/soc/mediatek/mt8192/pll.c
7 files changed, 32 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45401/1

diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index 1a2127d..b9c0d2c 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -57,7 +57,7 @@
    mt6358_init();
    /* Adjust VSIM2 down to 2.7V because it is shared with IT6505. */
    pmic_set_vsim2_cali(2700);
-	mt_pll_raise_ca53_freq(1989 * MHz);
+	mt_pll_raise_little_cpu_freq(1989 * MHz);
    pmic_init_scp_voltage();
    rtc_boot();
    mt_mem_init(&dparam_ops);
diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c
index e1d3747..2d62980 100644
--- a/src/mainboard/google/oak/romstage.c
+++ b/src/mainboard/google/oak/romstage.c
@@ -28,9 +28,9 @@

/* Set to maximum frequency */
    if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5)
-		mt_pll_raise_ca53_freq(1600 * MHz);
+		mt_pll_raise_little_cpu_freq(1600 * MHz);
    else
-		mt_pll_raise_ca53_freq(1700 * MHz);
+		mt_pll_raise_little_cpu_freq(1700 * MHz);

mtk_mmu_after_dram();
 }
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h
index a1bd96d..0f8732f 100644
--- a/src/soc/mediatek/common/include/soc/pll_common.h
+++ b/src/soc/mediatek/common/include/soc/pll_common.h
@@ -58,6 +58,6 @@
 void mux_set_sel(const struct mux *mux, u32 sel);
 int pll_set_rate(const struct pll *pll, u32 rate);
 void mt_pll_init(void);
-void mt_pll_raise_ca53_freq(u32 freq);
+void mt_pll_raise_little_cpu_freq(u32 freq);

#endif
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c
index 0fe94cf..7133fde 100644
--- a/src/soc/mediatek/mt8173/pll.c
+++ b/src/soc/mediatek/mt8173/pll.c
@@ -417,7 +417,7 @@
    }
 }

-void mt_pll_raise_ca53_freq(u32 freq)
+void mt_pll_raise_little_cpu_freq(u32 freq)
 {
    pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */
 }
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c
index 4570269..0e96f4c 100644
--- a/src/soc/mediatek/mt8183/pll.c
+++ b/src/soc/mediatek/mt8183/pll.c
@@ -362,7 +362,7 @@
    setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4);
 }

-void mt_pll_raise_ca53_freq(u32 freq)
+void mt_pll_raise_little_cpu_freq(u32 freq)
 {
    /* enable [4] intermediate clock armpll_divider_pll1_ck */
    setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h
index c83436e..177bd33 100644
--- a/src/soc/mediatek/mt8192/include/soc/pll.h
+++ b/src/soc/mediatek/mt8192/include/soc/pll.h
@@ -253,6 +253,7 @@

MCU_MUX_MASK = 0x3 << 9,
    MCU_MUX_SRC_PLL = 0x1 << 9,
+	MCU_MUX_SRC_DIV_PLL1 = 0x2 << 9,
 };

enum {
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index 40d92fd..e8849df 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -434,3 +434,28 @@
    /* enable [14] dramc_pll104m_ck */
    setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
 }
+
+void mt_pll_raise_little_cpu_freq(u32 freq)
+{
+	/* enable [4] intermediate clock armpll_divider_pll1_ck */
+	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+
+	/* switch ca55 clock source to intermediate clock */
+	clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1);
+
+	/* disable armpll_ll frequency output */
+	clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN);
+
+	/* raise armpll_ll frequency */
+	pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq);
+
+	/* enable armpll_ll frequency output */
+	setbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN);
+	udelay(PLL_EN_DELAY);
+
+	/* switch ca55 clock source back to armpll_ll */
+	clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+
+	/* disable [4] intermediate clock armpll_divider_pll1_ck */
+	clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+}

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45401 )

Change subject: soc/mediatek: Add function to raise the CPU frequency of MT8192
......................................................................

Patch Set 1: Code-Review+1

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45401 )

Change subject: soc/mediatek: Add function to raise the CPU frequency of MT8192
......................................................................

Patch Set 1: Code-Review+2

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45401 )

Change subject: soc/mediatek: Add function to raise the CPU frequency of MT8192
......................................................................

soc/mediatek: Add function to raise the CPU frequency of MT8192

Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq().
Implement mt_pll_raise_little_cpu_freq() in MT8192.

Signed-off-by: Weiyi Lu 
Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401
Tested-by: build bot (Jenkins) 
Reviewed-by: Hung-Te Lin 
Reviewed-by: Yu-Ping Wu 
---
M src/mainboard/google/kukui/romstage.c
M src/mainboard/google/oak/romstage.c
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8173/pll.c
M src/soc/mediatek/mt8183/pll.c
M src/soc/mediatek/mt8192/include/soc/pll.h
M src/soc/mediatek/mt8192/pll.c
7 files changed, 32 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, but someone else must approve
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index 1a2127d..b9c0d2c 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -57,7 +57,7 @@
    mt6358_init();
    /* Adjust VSIM2 down to 2.7V because it is shared with IT6505. */
    pmic_set_vsim2_cali(2700);
-	mt_pll_raise_ca53_freq(1989 * MHz);
+	mt_pll_raise_little_cpu_freq(1989 * MHz);
    pmic_init_scp_voltage();
    rtc_boot();
    mt_mem_init(&dparam_ops);
diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c
index e1d3747..2d62980 100644
--- a/src/mainboard/google/oak/romstage.c
+++ b/src/mainboard/google/oak/romstage.c
@@ -28,9 +28,9 @@

/* Set to maximum frequency */
    if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5)
-		mt_pll_raise_ca53_freq(1600 * MHz);
+		mt_pll_raise_little_cpu_freq(1600 * MHz);
    else
-		mt_pll_raise_ca53_freq(1700 * MHz);
+		mt_pll_raise_little_cpu_freq(1700 * MHz);

mtk_mmu_after_dram();
 }
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h
index a1bd96d..0f8732f 100644
--- a/src/soc/mediatek/common/include/soc/pll_common.h
+++ b/src/soc/mediatek/common/include/soc/pll_common.h
@@ -58,6 +58,6 @@
 void mux_set_sel(const struct mux *mux, u32 sel);
 int pll_set_rate(const struct pll *pll, u32 rate);
 void mt_pll_init(void);
-void mt_pll_raise_ca53_freq(u32 freq);
+void mt_pll_raise_little_cpu_freq(u32 freq);

#endif
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c
index 0fe94cf..7133fde 100644
--- a/src/soc/mediatek/mt8173/pll.c
+++ b/src/soc/mediatek/mt8173/pll.c
@@ -417,7 +417,7 @@
    }
 }

-void mt_pll_raise_ca53_freq(u32 freq)
+void mt_pll_raise_little_cpu_freq(u32 freq)
 {
    pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */
 }
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c
index 4570269..0e96f4c 100644
--- a/src/soc/mediatek/mt8183/pll.c
+++ b/src/soc/mediatek/mt8183/pll.c
@@ -362,7 +362,7 @@
    setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4);
 }

-void mt_pll_raise_ca53_freq(u32 freq)
+void mt_pll_raise_little_cpu_freq(u32 freq)
 {
    /* enable [4] intermediate clock armpll_divider_pll1_ck */
    setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h
index 442aa30..43c2528 100644
--- a/src/soc/mediatek/mt8192/include/soc/pll.h
+++ b/src/soc/mediatek/mt8192/include/soc/pll.h
@@ -249,6 +249,7 @@

MCU_MUX_MASK = 0x3 << 9,
    MCU_MUX_SRC_PLL = 0x1 << 9,
+	MCU_MUX_SRC_DIV_PLL1 = 0x2 << 9,
 };

enum {
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index 40d92fd..e8849df 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -434,3 +434,28 @@
    /* enable [14] dramc_pll104m_ck */
    setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
 }
+
+void mt_pll_raise_little_cpu_freq(u32 freq)
+{
+	/* enable [4] intermediate clock armpll_divider_pll1_ck */
+	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+
+	/* switch ca55 clock source to intermediate clock */
+	clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1);
+
+	/* disable armpll_ll frequency output */
+	clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN);
+
+	/* raise armpll_ll frequency */
+	pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq);
+
+	/* enable armpll_ll frequency output */
+	setbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN);
+	udelay(PLL_EN_DELAY);
+
+	/* switch ca55 clock source back to armpll_ll */
+	clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+
+	/* disable [4] intermediate clock armpll_divider_pll1_ck */
+	clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+}