Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53903 )
Change subject: libpayload: Add MMIO support in PCI lib ......................................................................
libpayload: Add MMIO support in PCI lib
Added MMIO Support in libpayload pci driver to allow ep config space access using payload PCI functions. endpoint config space addres passed from coreboot to payload through coreboot tables if MMIO supports.
Change-Id: I7cfb95e31b7ee984ee0c2e7586e6caeecd7deadd Signed-off-by: Prasad Malisetty pmaliset@codeaurora.org --- M payloads/libpayload/Kconfig M payloads/libpayload/configs/config.herobrine M payloads/libpayload/drivers/pci.c M payloads/libpayload/include/arm64/arch/io.h M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/soc/qualcomm/sc7280/Kconfig 11 files changed, 120 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/53903/1
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 7a502b5..8f67d2f 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -391,9 +391,13 @@
config PCI bool "Support for PCI devices" - depends on ARCH_X86 # for now default y
+config MMCONF_SUPPORT + bool "Support MMIO method" + depends on PCI + default y + config NVRAM bool "Support for reading/writing NVRAM bytes" depends on ARCH_X86 # for now diff --git a/payloads/libpayload/configs/config.herobrine b/payloads/libpayload/configs/config.herobrine index 6309d2b..c47afba 100644 --- a/payloads/libpayload/configs/config.herobrine +++ b/payloads/libpayload/configs/config.herobrine @@ -6,3 +6,6 @@ CONFIG_LP_USB_XHCI=y CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y +CONFIG_LP_MMCONF_SUPPORT=y +CONFIG_LP_PCI=y +CONFIG_LP_PCIE_NVME=y diff --git a/payloads/libpayload/drivers/pci.c b/payloads/libpayload/drivers/pci.c index 90e9220..326e0ed 100644 --- a/payloads/libpayload/drivers/pci.c +++ b/payloads/libpayload/drivers/pci.c @@ -32,38 +32,65 @@
u8 pci_read_config8(pcidev_t device, u16 reg) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + reg; + return read8(cfg_addr); +#endif outl(device | (reg & ~3), 0xCF8); return inb(0xCFC + (reg & 3)); }
u16 pci_read_config16(pcidev_t device, u16 reg) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + (reg & ~1); + return read16(cfg_addr); +#endif outl(device | (reg & ~3), 0xCF8); return inw(0xCFC + (reg & 3)); }
u32 pci_read_config32(pcidev_t device, u16 reg) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + (reg & ~3); + return read32(cfg_addr); +#endif outl(device | (reg & ~3), 0xCF8); return inl(0xCFC + (reg & 3)); }
void pci_write_config8(pcidev_t device, u16 reg, u8 val) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + (reg); + write8(cfg_addr, val); +#endif outl(device | (reg & ~3), 0xCF8); outb(val, 0xCFC + (reg & 3)); + return; }
void pci_write_config16(pcidev_t device, u16 reg, u16 val) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + (reg & ~1); + write16(cfg_addr, val); +#endif outl(device | (reg & ~3), 0xCF8); outw(val, 0xCFC + (reg & 3)); + return; }
void pci_write_config32(pcidev_t device, u16 reg, u32 val) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + (reg & ~3); + write32(cfg_addr, val); +#endif outl(device | (reg & ~3), 0xCF8); outl(val, 0xCFC + (reg & 3)); + return; }
static int find_on_bus(int bus, unsigned short vid, unsigned short did, diff --git a/payloads/libpayload/include/arm64/arch/io.h b/payloads/libpayload/include/arm64/arch/io.h index 9d67716..ae0bba1 100644 --- a/payloads/libpayload/include/arm64/arch/io.h +++ b/payloads/libpayload/include/arm64/arch/io.h @@ -133,4 +133,34 @@ dmb(); }
+static inline unsigned int inl(int port) +{ + return 0; +} + +static inline unsigned short inw(int port) +{ + return 0; +} + +static inline unsigned char inb(int port) +{ + return 0; +} + +static inline void outl(unsigned int val, int port) +{ + return; +} + +static inline void outw(unsigned short val, int port) +{ + return; +} + +static inline void outb(unsigned char val, int port) +{ + return; + +} #endif diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index e042a90..4e67a2c 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -86,6 +86,7 @@ CB_TAG_OPTION_ENUM = 0x00ca, CB_TAG_OPTION_DEFAULTS = 0x00cb, CB_TAG_OPTION_CHECKSUM = 0x00cc, + CB_TAG_PCI_EP_CONFIG = 0x00cd, };
struct cbuint64 { @@ -238,6 +239,13 @@ struct cb_gpio gpios[0]; };
+/* PCI EP config window info */ +struct cb_pci_config_info { + uint32_t tag; + uint32_t size; + void *config_base; +}; + struct lb_range { uint32_t tag; uint32_t size; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 5a24e14..b7e58fb 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -146,6 +146,7 @@
#if CONFIG(LP_PCI) struct pci_access pacc; + void *pci_ep_cfg_base; #endif };
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 7e23afe..d6f97f8 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -115,6 +115,13 @@ info->gpios[i] = gpios->gpios[i]; }
+static void cb_parse_pci_ep_config_base(void *ptr, struct sysinfo_t *info) +{ + struct cb_pci_config_info *pci = (struct cb_pci_config_info *)ptr; + + info->pci_ep_cfg_base = pci->config_base; +} + static void cb_parse_mac_addresses(unsigned char *ptr, struct sysinfo_t *info) { @@ -412,6 +419,9 @@ case CB_TAG_FMAP: cb_parse_fmap_cache(ptr, info); break; + case CB_TAG_PCI_EP_CONFIG: + cb_parse_pci_ep_config_base(ptr, info); + break; default: cb_parse_arch_specific(rec, info); break; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index be40c38..48e5ef5 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -89,6 +89,7 @@ LB_TAG_OPTION_ENUM = 0x00ca, LB_TAG_OPTION_DEFAULTS = 0x00cb, LB_TAG_OPTION_CHECKSUM = 0x00cc, + LB_TAG_PCI_EP_CONFIG = 0x00cd, };
/* Since coreboot is usually compiled 32bit, gcc will align 64bit @@ -326,6 +327,13 @@ struct lb_gpio gpios[0]; };
+/* PCI config info */ +struct lb_pci_config_info { + uint32_t tag; + uint32_t size; + void *config_base; +}; + struct lb_range { uint32_t tag; uint32_t size; diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index e77c60a..0240b87 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -21,6 +21,11 @@ void lb_add_serial(struct lb_serial *serial, void *data); void lb_add_console(uint16_t consoletype, void *data);
+/*Fill PCIe endpoint config window base address*/ +void lb_fill_ep_config_window(struct lb_pci_config_info *pci); +void lb_add_pci(struct lb_header *header); +void lb_add_pci_config(struct lb_pci_config_info *info, struct lb_pci_config_info *data); + /* Define this in mainboard.c to add board-specific table entries. */ void lb_board(struct lb_header *header);
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index cb85a18..7c89fc8 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -92,6 +92,21 @@ return mem; }
+void lb_add_pci_config(struct lb_pci_config_info *info, struct lb_pci_config_info *data) +{ + data->config_base = info->config_base; +} + +void lb_add_pci(struct lb_header *header) +{ + struct lb_pci_config_info *pci = NULL; + + pci = (struct lb_pci_config_info *)lb_new_record(header); + pci->tag = LB_TAG_PCI_EP_CONFIG; + pci->size = sizeof(*pci); + lb_fill_ep_config_window(pci); +} + void lb_add_serial(struct lb_serial *new_serial, void *data) { struct lb_header *header = (struct lb_header *)data; @@ -485,6 +500,10 @@ if (CONFIG(CHROMEOS)) lb_gpios(head);
+ /* Store MMCONF_BASE Address for ep config access */ + if (CONFIG(SC7280_PCIE_NVME)) + lb_add_pci(head); + /* pass along VBNV offsets in CMOS */ if (CONFIG(VBOOT_VBNV_CMOS)) lb_table_add_vbnv_cmos(head); diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index f182e9d..20d6289 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -45,4 +45,8 @@ help Select the QUP instance to be used for UART console output.
+config SC7280_PCIE_NVME + bool + default y + endif
-
Ravi kumar (Code Review)