Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 )
Change subject: mainboard/lenovo/t410: Add new port ......................................................................
Patch Set 21:
(4 comments)
A few nits, but looks good.
https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410/... File src/mainboard/lenovo/t410/Kconfig:
https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410/... PS21, Line 63: default 4
I think this should be 8
Clarckfield CPU's (quadcore) are supported by the current code. It could be a just a matter of adding the CPUID to the ramstage cpu code, or it could be the raminit does not work on it...
No wrongdoing in putting 8 here though.
https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410/... File src/mainboard/lenovo/t410/romstage.c:
https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410/... PS21, Line 54: : pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); : pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); : pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); : pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); Any idea if you need those during romstage as there is ramstage code to set those up based on dt (could be placed in romstage like on bd82x6x)
https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410/... File src/mainboard/lenovo/t410/vboot-rwa.fmd:
https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410/... PS21, Line 10: 0x16ffc0 I think you can drop this. It should fill the remaining space.
https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410/... PS21, Line 27: 0xff000 same
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Arthur Heymans (Code Review)