[XS] Change in coreboot[master]: [TEST] soc/intel/adl: disable SaGv low and high with gear2 for PnP an...

[Baieswara Reddy Sagili (Code Review)]

Baieswara Reddy Sagili has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79999?usp=email )

Change subject: [TEST] soc/intel/adl: disable SaGv low and high with gear2 for PnP anaysis
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[TEST] soc/intel/adl: disable SaGv low and high with gear2 for PnP anaysis

Change-Id: Ie3afed4dd313e6f9a0e802531c301e5e4cb56c96
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/79999/1

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
old mode 100644
new mode 100755
index 84f83e3..b1a9f1d
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -153,6 +153,9 @@
 static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
    	const struct soc_intel_alderlake_config *config)
 {
+	unsigned int i;
+	int sagv_freq[4] = {3733, 3733, 4267, 4267};
+
    m_cfg->SaGv = config->sagv;
    m_cfg->RMT = config->RMT;
    if (config->max_dram_speed_mts) {
@@ -163,6 +166,10 @@
    m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size;
    m_cfg->DisableSagvReorder = config->disable_sagv_reorder;
 #endif
+	for(i = 0; i < 4; i++) {
+		m_cfg->SaGvFreq[i] = sagv_freq[i];
+		m_cfg->SaGvGear[i] = 4;
+	}
 }

static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,