Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50335 )
Change subject: soc/intel/apollolake: Add romstage common stage file ......................................................................
soc/intel/apollolake: Add romstage common stage file
Change-Id: If4ed7c61494d2eb4652cfccb2602af8c180dbc57 Signed-off-by: Bernardo Perez Priego bernardo.perez.priego@intel.com --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/romstage.c 3 files changed, 46 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/50335/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 62049b5..de54c63 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -97,6 +97,8 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select UDELAY_TSC select TSC_MONOTONIC_TIMER + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_ROMSTAGE select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING if !SOC_INTEL_GEMINILAKE select UDK_2017_BINDING if SOC_INTEL_GEMINILAKE diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 64889e5..03f91ad 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -104,7 +104,7 @@ endif
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include - +CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include # Since FSP-M runs in CAR we need to relocate it to a specific address $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 0aa6c39..3b479d7 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -29,6 +29,7 @@ #include <spi_flash.h> #include <timer.h> #include "chip.h" +#include <intelbasecode/romstage.h>
static const uint8_t hob_variable_guid[16] = { 0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41, @@ -52,13 +53,15 @@ #define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0) #define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
+void romstage_pch_init(void) {/*Stub function*/} + /* * Enables several BARs and devices which are needed for memory init * - MCH_BASE_ADDR is needed in order to talk to the memory controller * - HPET is enabled because FSP wants to store a pointer to global data in the * HPET comparator register */ -static void soc_early_romstage_init(void) +void romstage_soc_init(void) { static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, @@ -155,37 +158,6 @@ cpu_set_p_state_to_turbo_ratio(); }
-void mainboard_romstage_entry(void) -{ - bool s3wake; - size_t var_size; - struct chipset_power_state *ps = pmc_get_power_state(); - const void *new_var_data; - - soc_early_romstage_init(); - report_platform_info(); - - s3wake = pmc_fill_power_state(ps) == ACPI_S3; - fsp_memory_init(s3wake); - - if (punit_init()) - set_max_freq(); - else - printk(BIOS_DEBUG, "Punit failed to initialize properly\n"); - - /* Stash variable MRC data and let cache system update it later */ - new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid, - &var_size); - if (new_var_data) - mrc_cache_stash_data(MRC_VARIABLE_DATA, - fsp_version, new_var_data, - var_size); - else - printk(BIOS_ERR, "Failed to determine variable data\n"); - - mainboard_save_dimm_info(); -} - static void fill_console_params(FSPM_UPD *mupd) { if (CONFIG(CONSOLE_SERIAL)) { @@ -229,8 +201,23 @@ } }
-static void soc_memory_init_params(FSPM_UPD *mupd) +static void parse_devicetree_setting(FSPM_UPD *m_upd) { + DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK); + +#if CONFIG(SOC_INTEL_GEMINILAKE) + m_upd->FspmConfig.TraceHubEn = dev ? dev->enabled : 0; +#else + m_upd->FspmConfig.NpkEn = dev ? dev->enabled : 0; +#endif +} + +void romstage_soc_mem_init_params(FSPM_UPD *mupd, uint32_t version) +{ + check_full_retrain(mupd); + + fill_console_params(mupd); + #if CONFIG(SOC_INTEL_GEMINILAKE) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -252,28 +239,11 @@ */ m_cfg->SkipPciePowerSequence = 1; #endif + fsp_version = version; }
-static void parse_devicetree_setting(FSPM_UPD *m_upd) +void romstage_mb_mem_init_params(FSPM_UPD *mupd) { - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK); - -#if CONFIG(SOC_INTEL_GEMINILAKE) - m_upd->FspmConfig.TraceHubEn = is_dev_enabled(dev); -#else - m_upd->FspmConfig.NpkEn = is_dev_enabled(dev); -#endif -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - check_full_retrain(mupd); - - fill_console_params(mupd); - - if (CONFIG(SOC_INTEL_GEMINILAKE)) - soc_memory_init_params(mupd); - mainboard_memory_init_params(mupd);
parse_devicetree_setting(mupd); @@ -309,19 +279,33 @@ */
mupd->FspmConfig.VariableNvsBufferPtr = - mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, version, + mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, fsp_version, NULL);
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - - fsp_version = version; - }
-__weak -void mainboard_memory_init_params(FSPM_UPD *mupd) +void romstage_soc_post_mem_init(void) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + const void *new_var_data; + size_t var_size; + + if (punit_init()) + set_max_freq(); + else + printk(BIOS_DEBUG, "Punit failed to initialize properly\n"); + + /* Stash variable MRC data and let cache system update it later */ + new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid, + &var_size); + if (new_var_data) + mrc_cache_stash_data(MRC_VARIABLE_DATA, + fsp_version, new_var_data, + var_size); + else + printk(BIOS_ERR, "Failed to determine variable data\n"); + + mainboard_save_dimm_info(); }
__weak