[S] Change in coreboot[main]: mb/asus/p8z77-m: Light DRAM_LED during early boot

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81890?usp=email )

Change subject: mb/asus/p8z77-m: Light DRAM_LED during early boot
......................................................................

mb/asus/p8z77-m: Light DRAM_LED during early boot

Turn on DRAM_LED on the mainboard in early bootblock, and turn it off
in ramstage. Primarily an indication if boot fails during raminit,
modeled after vendor firmware.

This LED is controlled by GPIO07 on the super I/O.

Boot tested on hardware.

Change-Id: I549b51375d1ef056d5fc01871bfe62d60b8a01cb
Signed-off-by: Keith Hui 
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
2 files changed, 17 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81890/1

diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
index 47c5cb3..78e0933 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

#include <bootblock_common.h>
+#include <device/pnp_ops.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/pei_data.h>
 #include <southbridge/intel/bd82x6x/pch.h>
@@ -11,6 +12,7 @@
 #include <option.h>

#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+#define GPIO0_DEV  PNP_DEV(0x2e, NCT6779D_WDT1_GPIO01_V)

const struct southbridge_usb_port mainboard_usb_ports[] = {
    /* {enable, current, oc_pin} */
@@ -34,6 +36,17 @@
 {
    nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

+	nuvoton_pnp_enter_conf_state(GPIO0_DEV);
+
+	/* Turn on DRAM_LED. If raminit dies, this would remain on and we know
+	 * we have a problem. We turn it off in ramstage. */
+	pnp_set_logical_device(GPIO0_DEV);
+	pnp_write_config(GPIO0_DEV, 0x30, 0x02);
+	pnp_write_config(GPIO0_DEV, 0xe0, 0x7f);
+	pnp_write_config(GPIO0_DEV, 0xe1, 0x00);
+
+	nuvoton_pnp_exit_conf_state(GPIO0_DEV);
+
    /*
     * TODO: Put PCIe root port 7 (00:1c.6) into subtractive decode and have it accept I/O
     * cycles. This should allow a POST card in the PCI slot, connected via an ASM1083
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index ee2fe9a..f6b3577 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -48,6 +48,10 @@
    				end
    				device pnp 2e.6 off end		# CIR
    				device pnp 2e.8 off end		# WDT1
+					device pnp 2e.108 on		# GPIO 0
+						drq 0xe0 = 0x7f		# GP07 output
+						drq 0xe1 = 0x80		# GP07 high turns DRAM_LED off
+					end
    				device pnp 2e.a on		# ACPI
    					drq 0xe4 = 0x10 	# Enable 3VSBSW#, needed for S3 suspend
    					drq 0xe7 = 0x11		# HWM reset by LRESET#, 0.5s S3 delay for compatibility
@@ -66,7 +70,6 @@
    				end
    				device pnp 2e.9 off end		# GPIO 8
    				device pnp 2e.308 on end	# GPIO by I/O
-					device pnp 2e.108 on end	# GPIO 0
    				device pnp 2e.109 on end	# GPIO 1
    				device pnp 2e.209 on		# GPIO 2
    					drq 0xe0 = 0xbf		# GP26 output