Change in coreboot[master]: [RFC] ChromeOS, VBOOT: Add VBOOT_NVS

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Lance Zhao, Martin Roth, Aaron Durbin, Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50611 )

Change subject: [RFC] ChromeOS, VBOOT: Add VBOOT_NVS
......................................................................

[RFC] ChromeOS, VBOOT: Add VBOOT_NVS

Allows addition of VBOOT hash variables in ACPI space without
selected CHROMEOS.

Change-Id: Ife888ae43093949bb2d3e397565033037396f434
Signed-off-by: Kyösti Mälkki 
---
M src/acpi/Makefile.inc
M src/acpi/acpigen_extern.asl
M src/acpi/dsdt_top.asl
M src/acpi/gnvs.c
M src/arch/x86/smbios.c
M src/mainboard/google/butterfly/acpi_tables.c
M src/mainboard/google/parrot/acpi_tables.c
M src/mainboard/google/stout/acpi_tables.c
M src/mainboard/samsung/lumpy/acpi_tables.c
M src/security/vboot/Kconfig
M src/soc/intel/broadwell/pch/me.c
M src/southbridge/intel/bd82x6x/me_common.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/vendorcode/google/chromeos/Kconfig
M src/vendorcode/google/chromeos/Makefile.inc
M src/vendorcode/google/chromeos/ramoops.c
16 files changed, 22 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/50611/1

diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc
index 86f29e4..b703680 100644
--- a/src/acpi/Makefile.inc
+++ b/src/acpi/Makefile.inc
@@ -9,7 +9,7 @@
 ramstage-y += acpigen_ps2_keybd.c
 ramstage-y += acpigen_usb.c
 ramstage-y += device.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos-gnvs.c
+ramstage-$(CONFIG_VBOOT_NVS) += chromeos-gnvs.c
 ramstage-$(CONFIG_ACPI_SOC_NVS) += gnvs.c
 ramstage-y += pld.c
 ramstage-y += sata.c
diff --git a/src/acpi/acpigen_extern.asl b/src/acpi/acpigen_extern.asl
index 5e380b5..0d9081c 100644
--- a/src/acpi/acpigen_extern.asl
+++ b/src/acpi/acpigen_extern.asl
@@ -19,7 +19,7 @@
 OperationRegion (DNVS, SystemMemory, NVB1, NVS1)
 #endif

-#if CONFIG(CHROMEOS)
+#if CONFIG(VBOOT_NVS)
 External (NVB2, IntObj)
 External (NVS2, IntObj)
 OperationRegion (CNVS, SystemMemory, NVB2, NVS2)
diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl
index 4300f0a..61ef1ae 100644
--- a/src/acpi/dsdt_top.asl
+++ b/src/acpi/dsdt_top.asl
@@ -2,7 +2,7 @@

#include <acpi/acpigen_extern.asl>

-#if CONFIG(CHROMEOS)
+#if CONFIG(VBOOT_NVS)
 /* Chrome OS specific */
 #include <vendorcode/google/chromeos/acpi/gnvs.asl>
 #include <vendorcode/google/chromeos/acpi/chromeos.asl>
diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c
index 63740d0..2dbfa4a 100644
--- a/src/acpi/gnvs.c
+++ b/src/acpi/gnvs.c
@@ -26,7 +26,7 @@
    	gnvs_size = 0x100;
    if (CONFIG(ACPI_HAS_DEVICE_NVS))
    	gnvs_size = 0x2000;
-	else if (CONFIG(CHROMEOS))
+	else if (CONFIG(VBOOT_NVS))
    	gnvs_size = 0x1000;

gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size);
@@ -38,7 +38,7 @@
    if (CONFIG(CONSOLE_CBMEM))
    	gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);

-	if (CONFIG(CHROMEOS))
+	if (CONFIG(VBOOT_NVS))
    	gnvs_assign_chromeos((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
 }

@@ -78,7 +78,7 @@
    acpigen_write_name_dword("NVS0", 0x100);
    acpigen_pop_len();

-	if (CONFIG(CHROMEOS)) {
+	if (CONFIG(VBOOT_NVS)) {
    	acpigen_write_scope("\");
    	acpigen_write_name_dword("NVB2", (uintptr_t)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
    	acpigen_write_name_dword("NVS2", 0xf00);
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 8bc49b1..508a393 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -422,7 +422,7 @@
    t->vendor = smbios_add_string(t->eos, "coreboot");
    t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);

-	if (CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES)) {
+	if (CONFIG(VBOOT_NVS)) {
    	uintptr_t version_address = (uintptr_t)t->eos;
    	/* SMBIOS offsets start at 1 rather than 0 */
    	version_address += (u32)smbios_string_table_len(t->eos) - 1;
diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c
index 29faea3..66e1c31 100644
--- a/src/mainboard/google/butterfly/acpi_tables.c
+++ b/src/mainboard/google/butterfly/acpi_tables.c
@@ -18,7 +18,7 @@
    // The firmware read/write status is a "virtual" switch and
    // will be handled elsewhere.  Until then hard-code to
    // read/write instead of read-only for developer mode.
-	if (CONFIG(CHROMEOS))
+	if (CONFIG(VBOOT_NVS))
    	gnvs_set_ecfw_rw();

// the lid is open by default.
diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c
index 1cb4597..d3973c1 100644
--- a/src/mainboard/google/parrot/acpi_tables.c
+++ b/src/mainboard/google/parrot/acpi_tables.c
@@ -21,7 +21,7 @@
    gnvs->s5u0 = 0;
    gnvs->s5u1 = 0;

-	if (CONFIG(CHROMEOS) && !parrot_ec_running_ro())
+	if (CONFIG(VBOOT_NVS) && !parrot_ec_running_ro())
    	gnvs_set_ecfw_rw();

/* EC handles all active thermal and fan control on Parrot. */
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
index fe12e30..864178d 100644
--- a/src/mainboard/google/stout/acpi_tables.c
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -22,7 +22,7 @@
    gnvs->s5u0 = 0;
    gnvs->s5u1 = 0;

-	if (CONFIG(CHROMEOS) && !get_recovery_mode_switch())
+	if (CONFIG(VBOOT_NVS) && !get_recovery_mode_switch())
    	gnvs_set_ecfw_rw();

/* EC handles all thermal and fan control on Stout. */
diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c
index c697457..07c1fbc 100644
--- a/src/mainboard/samsung/lumpy/acpi_tables.c
+++ b/src/mainboard/samsung/lumpy/acpi_tables.c
@@ -44,6 +44,6 @@
    gnvs->tmax = MAX_TEMPERATURE;
    gnvs->flvl = 5;

-	if (CONFIG(CHROMEOS) && ec_read(0xcb))
+	if (CONFIG(VBOOT_NVS) && ec_read(0xcb))
    	gnvs_set_ecfw_rw();
 }
diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig
index e202333..b09508f 100644
--- a/src/security/vboot/Kconfig
+++ b/src/security/vboot/Kconfig
@@ -71,6 +71,11 @@
    help
      VBNV is stored in flash storage

+config VBOOT_NVS
+	bool
+	default n
+	depends on HAVE_ACPI_TABLES
+
 config VBOOT_STARTS_BEFORE_BOOTBLOCK
    def_bool n
    select VBOOT_SEPARATE_VERSTAGE
diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c
index 88d2172..97e062f 100644
--- a/src/soc/intel/broadwell/pch/me.c
+++ b/src/soc/intel/broadwell/pch/me.c
@@ -770,7 +770,7 @@
    printk(BIOS_DEBUG, "\n");

/* Save hash in NVS for the OS to verify */
-	if (CONFIG(CHROMEOS))
+	if (CONFIG(VBOOT_NVS))
    	chromeos_set_me_hash(extend, count);

return 0;
diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c
index e229956..64c372f 100644
--- a/src/southbridge/intel/bd82x6x/me_common.c
+++ b/src/southbridge/intel/bd82x6x/me_common.c
@@ -405,7 +405,7 @@
    printk(BIOS_DEBUG, "\n");

/* Save hash in NVS for the OS to verify */
-	if (CONFIG(CHROMEOS))
+	if (CONFIG(VBOOT_NVS))
    	chromeos_set_me_hash(extend, count);

return 0;
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 69192e6..366e3bc 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -753,7 +753,7 @@
    printk(BIOS_DEBUG, "\n");

/* Save hash in NVS for the OS to verify */
-	if (CONFIG(CHROMEOS))
+	if (CONFIG(VBOOT_NVS))
    	chromeos_set_me_hash(extend, count);

return 0;
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index e81f31d..88eab8c 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -12,6 +12,7 @@
    select ELOG if BOOT_DEVICE_SUPPORTS_WRITES
    select COLLECT_TIMESTAMPS
    select VBOOT
+	select VBOOT_NVS
    select VPD
    select VBOOT_SLOTS_RW_AB
    help
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index ba00d77..74534ef 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -1,7 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only

ramstage-$(CONFIG_ELOG) += elog.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c
+ramstage-$(CONFIG_VBOOT_NVS) += gnvs.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c
 ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c
diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c
index 77e079f..54bad45 100644
--- a/src/vendorcode/google/chromeos/ramoops.c
+++ b/src/vendorcode/google/chromeos/ramoops.c
@@ -38,7 +38,7 @@
    	return;
    }

-	if (CONFIG(HAVE_ACPI_TABLES))
+	if (CONFIG(VBOOT_NVS))
    	set_ramoops(ram_oops, size);
 }