[XS] Change in coreboot[main]: soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78252?usp=email )

Change subject: soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly
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soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly

The original code only reserves IOM mmio, but there is other asl
code requires to program ioe p2sb mmio such as IOE PCIE clk request
control. See _SB.ECLK.CLKD insrc/soc/intel/common/acpi/pcie_clk.asl

TEST=suspend_stress_test 50 cycle pass, type-c display OK on screebo

Change-Id: Ie55f7975277b390f776e44596c42e426ba9cd235
Signed-off-by: Kane Chen 
---
M src/soc/intel/meteorlake/p2sb.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/78252/1

diff --git a/src/soc/intel/meteorlake/p2sb.c b/src/soc/intel/meteorlake/p2sb.c
index ae9b9a4..761bb26 100644
--- a/src/soc/intel/meteorlake/p2sb.c
+++ b/src/soc/intel/meteorlake/p2sb.c
@@ -35,7 +35,7 @@
 static void ioe_p2sb_read_resources(struct device *dev)
 {
    /* Add the fixed MMIO resource for IOM */
-	mmio_range(dev, PCI_BASE_ADDRESS_0, IOM_BASE_ADDR, IOM_BASE_SIZE);
+	mmio_range(dev, PCI_BASE_ADDRESS_0, IOE_P2SB_BAR, IOE_P2SB_SIZE);
 }

static void p2sb_read_resources(struct device *dev)