Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29872

Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
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mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group

We discovered that the gpios previously used for FPMCU_INT_L were in
two different groups with two different voltages (C group was at 3.3V
and D group was at 1.8V).  Moving both to B group which is at 3.3V.

BUG=b:119447525
BRANCH=Nami
TEST=unlock OS with fingerprint
     register fingerprint
     run powerd_dbus_suspend and see if it goes int s0ix

Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071
Signed-off-by: Shelley Chen 
---
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nami/gpio.c
2 files changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29872/1

diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 49e35b2..cd57398 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -455,8 +455,8 @@
    			register "hid" = "ACPI_DT_NAMESPACE_HID"
    			register "uid" = "1"
    			register "compat_string" = ""google,cros-ec-spi""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)"
-				register "wake" = "GPE0_DW1_06" # GPP_D6
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B0_IRQ)"
+				register "wake" = "GPE0_DW0_01" # GPP_B1
    			device spi 0 on end
    		end # FPMCU
    	end # GSPI #1
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
index 2c9b932..0fa25a8 100644
--- a/src/mainboard/google/poppy/variants/nami/gpio.c
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -421,14 +421,14 @@
    PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
    /* C3  : SML0CLK ==> TOUCHSCREEN_DIS# */
    PAD_CFG_GPO(GPP_C3, 0, DEEP),
-	/* C8  : UART0_RXD ==> FPMCU_INT_L */
-	PAD_CFG_GPI_APIC(GPP_C8, NONE, DEEP),
+	/* B0  : CORE_VID0 ==> FPMCU_INT_L */
+	PAD_CFG_GPI_APIC(GPP_B0, NONE, DEEP),
    /* C9  : UART0_TXD ==> FP_RST_ODL */
    PAD_CFG_GPO(GPP_C9, 1, DEEP),
    /* D5  : ISH_I2C0_SDA ==> FPMCU_BOOT0 */
    PAD_CFG_GPO(GPP_D5, 0, DEEP),
-	/* D6  : ISH_I2C0_SCL ==> FPMCU_INT_L */
-	PAD_CFG_GPI_ACPI_SCI(GPP_D6, 20K_PU, DEEP, INVERT),
+	/* B1  : CORE_VID1 ==> FPMCU_INT_L */
+	PAD_CFG_GPI_ACPI_SCI(GPP_B1, 20K_PU, DEEP, INVERT),
    /* D17 : DMIC_CLK1 ==> NC */
    PAD_CFG_NC(GPP_D17),
 };