New patch to review for coreboot: x86: prepare cache-as-ram to allow multiple stages

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11740

-gerrit

commit aa3e6ab0b12ce7b6fee96c8655d81fa682fa2c8f
Author: Aaron Durbin 
Date:   Thu Sep 24 12:18:07 2015 -0500

x86: prepare cache-as-ram to allow multiple stages

In order to do a verification of romstage on x86 one needs to
    run verstage which verifies romstage (and the memory init code).
    However, x86 doesn't have SRAM like every other modern SoC so
    managing the cache-as-ram region is especially critical.

First move all of the "shared" objects to the beginning of
    the .car.data section. This change then ensures that each stage
    using car.ld to link has the same consistent view of the addresses
    of these fixed-sized objects in cache-as-ram. The CAR_GLOBALs can
    be unique per stage. However, these variables are expected to have
    a value of zero at the start of each stage. In order to allow a
    stage to provide those semantics outside of the initial cache-as-arm
    setup routine add _car_global_start and _car_global_end symbols.
    Those symbols can be used to clear the CAR_GLOBALs for that stage.

Note that the timestamp region can't be moved out similarly to the
    pre-ram cbmem console because the object storage of the timestamp
    cache is used *after* cache-as-ram is torn down to indicate if the
    cache should be used or not. Therefore, that timestamp needs to
    migrated to ram. A logic change in src/lib/timestamp.c could
    alleviate this requirement, but that task wasn't tackled in this
    patch.

BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.

Change-Id: I15e9f6b0c632ee5a2369da0709535d6cb0d94f61
    Signed-off-by: Aaron Durbin 
---
 src/arch/x86/car.ld | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index c30c802..5da9dcf 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -22,15 +22,29 @@
 /* This file is included inside a SECTIONS block */
 . = CONFIG_DCACHE_RAM_BASE;
 .car.data . (NOLOAD) : {
+	/* The pre-ram cbmem console as well as the timestamp region are fixed
+	 * in size. Therefore place them at the beginning .car.data section
+	 * so that multiple stages (romstage and verstage) have a consistent
+	 * link address of these shared objects. */
+	PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
    _car_data_start = .;
+	/* The timestamp implementation relies on this storage to be around
+	 * after migration. One of the fields indicates not to use it as the
+	 * backing store once cbmem comes online. Therefore, this data needs
+	 * to reside in the migrated area (between _car_data_start and
+	 * _car_data_end). */
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
    TIMESTAMP(., 0x100)
 #endif
+	/* _car_global_start and _car_global_end provide symbols to per-stage
+	 * variables that are not shared like the timestamp and the pre-ram
+	 * cbmem console. This is useful for clearing this area on a per-stage
+	 * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
+	_car_global_start = .;
    *(.car.global_data);
    . = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_car_global_end = .;
    _car_data_end = .;
-
-	PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 }

/* Global variables are not allowed in romstage
@@ -48,4 +62,4 @@
    *(.sbss.*)
 }

-_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
+_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");