Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35134 )
Change subject: ipq40xx: Increase CBFS and RAMSTAGE size. ......................................................................
ipq40xx: Increase CBFS and RAMSTAGE size.
Increase CBFS and RAMSTAGE size to accommodate larger binary component.
BUG=b:77641795 TEST=Build and test on Gale. BRANCH=none
Change-Id: I25f7121221ab2bb66dfedbc4a66e06976d88cef5 Signed-off-by: Patrick Georgi pgeorgi@google.com Original-Commit-Id: e4d3d2d078d0a8f705afe2b6c741118727614bf0 Original-Change-Id: I6ad16c0073a683cb66d5ae8a46b8990f3346f183 Original-Signed-off-by: Kan Yan kyan@google.com Original-Reviewed-on: https://chromium-review.googlesource.com/1366388 Original-Reviewed-by: Zhihong Yu zhihongyu@chromium.org --- M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/35134/1
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index a69b60b..f1a7bc5 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -58,7 +58,7 @@
DRAM_START(0x80000000) SYMBOL(memlayout_cbmem_top, 0x87280000) - POSTRAM_CBFS_CACHE(0x87280000, 384K) - RAMSTAGE(0x872e0000, 128K) - DMA_COHERENT(0x87300000, 2M) + POSTRAM_CBFS_CACHE(0x87280000, 512K) + RAMSTAGE(0x87300000, 512K) + DMA_COHERENT(0x87400000, 2M) }
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35134 )
Change subject: ipq40xx: Increase CBFS and RAMSTAGE size. ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35134/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35134/1//COMMIT_MSG@7 PS1, Line 7: ipq40xx: Increase CBFS and RAMSTAGE size. Please remove the dot/period at the end.
Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35134
to look at the new patch set (#2).
Change subject: ipq40xx: Increase CBFS and RAMSTAGE size ......................................................................
ipq40xx: Increase CBFS and RAMSTAGE size
Increase CBFS and RAMSTAGE size to accommodate larger binary component.
BUG=b:77641795 TEST=Build and test on Gale. BRANCH=none
Change-Id: I25f7121221ab2bb66dfedbc4a66e06976d88cef5 Signed-off-by: Patrick Georgi pgeorgi@google.com Original-Commit-Id: e4d3d2d078d0a8f705afe2b6c741118727614bf0 Original-Change-Id: I6ad16c0073a683cb66d5ae8a46b8990f3346f183 Original-Signed-off-by: Kan Yan kyan@google.com Original-Reviewed-on: https://chromium-review.googlesource.com/1366388 Original-Reviewed-by: Zhihong Yu zhihongyu@chromium.org --- M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/35134/2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35134 )
Change subject: ipq40xx: Increase CBFS and RAMSTAGE size ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35134/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35134/1//COMMIT_MSG@7 PS1, Line 7: ipq40xx: Increase CBFS and RAMSTAGE size.
Please remove the dot/period at the end.
Done
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35134 )
Change subject: ipq40xx: Increase CBFS and RAMSTAGE size ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35134 )
Change subject: ipq40xx: Increase CBFS and RAMSTAGE size ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35134 )
Change subject: ipq40xx: Increase CBFS and RAMSTAGE size ......................................................................
ipq40xx: Increase CBFS and RAMSTAGE size
Increase CBFS and RAMSTAGE size to accommodate larger binary component.
BUG=b:77641795 TEST=Build and test on Gale. BRANCH=none
Change-Id: I25f7121221ab2bb66dfedbc4a66e06976d88cef5 Signed-off-by: Patrick Georgi pgeorgi@google.com Original-Commit-Id: e4d3d2d078d0a8f705afe2b6c741118727614bf0 Original-Change-Id: I6ad16c0073a683cb66d5ae8a46b8990f3346f183 Original-Signed-off-by: Kan Yan kyan@google.com Original-Reviewed-on: https://chromium-review.googlesource.com/1366388 Original-Reviewed-by: Zhihong Yu zhihongyu@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/35134 Reviewed-by: Julius Werner jwerner@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index a69b60b..f1a7bc5 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -58,7 +58,7 @@
DRAM_START(0x80000000) SYMBOL(memlayout_cbmem_top, 0x87280000) - POSTRAM_CBFS_CACHE(0x87280000, 384K) - RAMSTAGE(0x872e0000, 128K) - DMA_COHERENT(0x87300000, 2M) + POSTRAM_CBFS_CACHE(0x87280000, 512K) + RAMSTAGE(0x87300000, 512K) + DMA_COHERENT(0x87400000, 2M) }
-
Angel Pons (Code Review) -
Julius Werner (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)