Change in coreboot[master]: soc/amd: Make espi_configure_decodes private

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52059 )

Change subject: soc/amd: Make espi_configure_decodes private
......................................................................

soc/amd: Make espi_configure_decodes private

This is only ever called after espi_setup.

55861 - AMD System Peripheral Bus Overview also says that io ranges
should be configured before enabling the BUS_MASTER bit.

BUG=b:183524609
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel 
Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269
---
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/common/block/include/amdblocks/espi.h
M src/soc/amd/common/block/lpc/espi_util.c
M src/soc/amd/picasso/early_fch.c
M src/soc/amd/picasso/psp_verstage/fch.c
5 files changed, 6 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/52059/1

diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index 0c72863..5dca211 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -67,8 +67,6 @@
    if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
    	lpc_disable_spi_rom_sharing();

-	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
    	espi_setup();
-		espi_configure_decodes();
-	}
 }
diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h
index c593e02..435b81f 100644
--- a/src/soc/amd/common/block/include/amdblocks/espi.h
+++ b/src/soc/amd/common/block/include/amdblocks/espi.h
@@ -101,12 +101,6 @@
 int espi_open_mmio_window(uint32_t base, size_t size);

/*
- * Configure generic and standard I/O decode windows using the espi_config structure settings
- * provided by mainboard in device tree.
- */
-void espi_configure_decodes(void);
-
-/*
  * In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading
  * SPIBASE. This is required for cases where verstage runs on PSP.
  */
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 5fa2058..dd81c5f 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -277,10 +277,9 @@
    return &soc_cfg->espi_config;
 }

-void espi_configure_decodes(void)
+static void espi_configure_decodes(const struct espi_config *cfg)
 {
    int i;
-	const struct espi_config *cfg = espi_get_config();

espi_enable_decode(cfg->std_io_decode_bitmap);

@@ -945,6 +944,8 @@
    	return -1;
    }

+	espi_configure_decodes(cfg);
+
    /* Enable subtractive decode if configured */
    espi_setup_subtractive_decode(cfg);

diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c
index 63e192f..5f47638 100644
--- a/src/soc/amd/picasso/early_fch.c
+++ b/src/soc/amd/picasso/early_fch.c
@@ -77,8 +77,6 @@
    if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
    	lpc_disable_spi_rom_sharing();

-	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
    	espi_setup();
-		espi_configure_decodes();
-	}
 }
diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c
index e6c70f6..a032bde 100644
--- a/src/soc/amd/picasso/psp_verstage/fch.c
+++ b/src/soc/amd/picasso/psp_verstage/fch.c
@@ -153,8 +153,6 @@

void verstage_soc_init(void)
 {
-	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
    	espi_setup();
-		espi_configure_decodes();
-	}
 }