[XS] Change in coreboot[main]: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8

[Robert Chen (Code Review)]

Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85011?usp=email )

Change subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
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mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8

Realtek AX generation IC utilizes LTR-issued latency requests to
optimize WiFi latency and power consumption, it requires host
enabling LTR to meet the design requirement. We enabled the host's
LTR by enabling PCIe root port 8, which met resltek's technical
requirements.

BUG=b:377400590
TEST=Tested on Drawman with RTL8852BE
Use command $ lspci -vv, LTR+ is listed on DevCtl2
BRANCH=firmware-dedede-13606.B

SSigned-off-by: Robert Chen 
Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe
---
M src/mainboard/google/dedede/variants/drawcia/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/85011/1

diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index 67c9262..6c745d9 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -7,6 +7,9 @@
 end
 chip soc/intel/jasperlake

+	# PCIe RP LTR configuration
+	register "PcieRpLtrEnable[7]" = "1"
+
    # USB Port Configuration
    register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"     # Camera