Change in ...coreboot[master]: soc/amd/stoneyridge/gpio: Disable mask_sts when configuring GPIOs

[Daniel Kurtz (Code Review)]

Hello Daniel Kurtz,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/31000

to review the following change.

Change subject: soc/amd/stoneyridge/gpio: Disable mask_sts when configuring GPIOs
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soc/amd/stoneyridge/gpio: Disable mask_sts when configuring GPIOs

Disable mask_sts and GPIO interrupt enable when confiuring GPIOs.  The
mask_sts bits control a feature that temporarily disables GPIO interrupt
delivery for ALL GPIOs whenever the debounce registers of any one GPIO
are changed.  This feature is supposed to eliminate the possibility of
spurious interrupts when changing debounce.  The period for which
interrupts are disabled is about 4 ms.

This feature is not needed when configuring GPIOs in coreboot for we do
not expect to have any active GPIO interrupt sources at this point.
Furthermore, we also disable IRQ interrupts to elimintate the
possibility of a spurious event while mask_sts is disabled.

Together this allows us to safely and quickly configure the gpio
debounce registers while configuring GPIOs.

Signed-off-by: Daniel Kurtz

BUG=b:113880780
BRANCH=none
TEST=Reboot stress test grunt (>100 times); no messages in dmesg like:
  tpm tpm0: Timeout waiting for TPM ready

Change-Id: I9cd1f809687e7933ffbf7a83b69d603104d66bee
---
M src/soc/amd/stoneyridge/gpio.c
M src/soc/amd/stoneyridge/include/soc/gpio.h
2 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31000/1

diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index 955cc6a..fc7ed67 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -227,6 +227,23 @@
    uint32_t mask, bit_edge, bit_level;
    uint8_t mux, index, gpio;
    int gevent_num;
+	uint32_t *gpio_xfc;
+	uint32_t gpio_xfc_init;
+
+	/*
+	 * Disable hardware "irq disable on debounce write" feature while
+	 * configuring GPIOs.  This avoids needing to wait 4 ms after
+	 * configuring the debounce registers on any gpio.  If we don't do this
+	 * then modifying debounce registers would cause irq enable bits to
+	 * read as 0, potentially permanently disabling irqs during RMW
+	 * operations. This is safe to do here, since no GPIO interrupts are
+	 * disabled at this point (and we explicitly disable them to avoid any
+	 * spurious IRQs due to changing debounce settings).
+	 */
+	gpio_xfc = (uint32_t *)(uintptr_t)GPIO_WAKE_INTER_MASTER_SWITCH;
+	gpio_xfc_init = read32(gpio_xfc);
+	write32(gpio_xfc,
+		gpio_xfc_init & ~(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN));

direction = 0;
    edge_level = 0;
@@ -297,6 +314,8 @@
    /* Set all SCI trigger level (edge/level) */
    mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_LEVEL),
    				edge_level, mask);
+
+	write32(gpio_xfc, gpio_xfc_init);
 }

/*
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index 47eae84..c9e9b16 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -182,6 +182,11 @@
 #define GPIO_147			147
 #define GPIO_148			148

+/* GPIOxFC GPIO_Wake_Inter_Master Switch */
+#define GPIO_WAKE_INTER_MASTER_SWITCH	(AMD_SB_ACPI_MMIO_ADDR + 0x15fc)
+# define GPIO_INTERRUPT_EN		(1 << 30)
+# define GPIO_MASK_STS_EN		(1 << 28)
+
 #define I2C0_SCL_PIN			GPIO_145
 #define I2C1_SCL_PIN			GPIO_147
 #define I2C2_SCL_PIN			GPIO_113

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31000 )

Change subject: soc/amd/stoneyridge/gpio: Disable mask_sts when configuring GPIOs
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Patch Set 1: Code-Review+2

[Daniel Kurtz (Code Review)]

Daniel Kurtz has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31000 )

Change subject: soc/amd/stoneyridge/gpio: Disable mask_sts when configuring GPIOs
......................................................................

Abandoned

obsolete by CL:31082