Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27408
Change subject: src/soc: Use "foo *bar" instead of "foo* bar" ......................................................................
src/soc: Use "foo *bar" instead of "foo* bar"
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/ramstage.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_broadwell_de/pmutil.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/me.c M src/soc/nvidia/tegra/dc.h M src/soc/nvidia/tegra124/clock.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra124/include/soc/clock.h M src/soc/nvidia/tegra210/clock.c M src/soc/nvidia/tegra210/dc.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/flow_ctrl.c M src/soc/nvidia/tegra210/include/soc/id.h M src/soc/nvidia/tegra210/mtc.c M src/soc/nvidia/tegra210/power.c M src/soc/qualcomm/ipq806x/usb.c M src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h M src/soc/samsung/exynos5250/include/soc/power.h M src/soc/samsung/exynos5420/dp_lowlevel.c M src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h M src/soc/samsung/exynos5420/include/soc/power.h M src/soc/samsung/exynos5420/smp.c 31 files changed, 79 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/27408/1
diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 92d27dc..3a55244 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -31,7 +31,7 @@
struct irq_idx_name { uint8_t index; - const char * const name; + const char *const name; };
extern const struct pirq_struct *pirq_data_ptr; diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index a3f1fc7..ba12c8f 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -31,7 +31,7 @@
void mainboard_romstage_entry(struct romstage_params *params); void romstage_common(struct romstage_params *params); -void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo, +void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo, uint32_t tsc_high); void asmlinkage romstage_after_car(void); void raminit(struct mrc_params *mp, int prev_sleep_state); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index e38957e..c971b35 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -98,7 +98,7 @@ }
/* Entry from cache-as-ram.inc. */ -void * asmlinkage romstage_main(unsigned long bist, +void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, uint32_t tsc_hi) { struct romstage_params rp = { diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 5f078df..00284d1 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -53,7 +53,7 @@ }
static void print_num_status_bits(int num_bits, uint32_t status, - const char * const bit_names[]) + const char *const bit_names[]) { int i;
@@ -72,7 +72,7 @@
static uint32_t print_smi_status(uint32_t smi_sts) { - static const char * const smi_sts_bits[] = { + static const char *const smi_sts_bits[] = { [2] = "BIOS", [4] = "SLP_SMI", [5] = "APM", @@ -157,7 +157,7 @@
static uint16_t print_pm1_status(uint16_t pm1_sts) { - static const char * const pm1_sts_bits[] = { + static const char *const pm1_sts_bits[] = { [0] = "TMROF", [5] = "GBL", [8] = "PWRBTN", @@ -190,7 +190,7 @@
static uint32_t print_tco_status(uint32_t tco_sts) { - static const char * const tco_sts_bits[] = { + static const char *const tco_sts_bits[] = { [3] = "TIMEOUT", [17] = "SECOND_TO", }; @@ -252,7 +252,7 @@
static uint32_t print_gpe_sts(uint32_t gpe_sts) { - static const char * const gpe_sts_bits[] = { + static const char *const gpe_sts_bits[] = { [1] = "HOTPLUG", [2] = "SWGPE", [3] = "PCIE_WAKE0", @@ -308,7 +308,7 @@ static uint32_t print_alt_sts(uint32_t alt_gpio_smi) { uint32_t alt_gpio_sts; - static const char * const alt_gpio_smi_sts_bits[] = { + static const char *const alt_gpio_smi_sts_bits[] = { [0] = "SUS_GPIO_0", [1] = "SUS_GPIO_1", [2] = "SUS_GPIO_2", diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 3ab1af3..4559739 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -72,7 +72,7 @@ } }
-static const char * const stepping_str[] = { +static const char *const stepping_str[] = { "A0", "A1", "B0", "B1", "B2", "B3", "C0" };
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index a2cd864..9d967ce 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -86,7 +86,7 @@ char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ int vt, txt, aes; msr_t microcode_ver; - static const char * const mode[] = {"NOT ", ""}; + static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; u32 p[13];
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index ddf384b..9b21010 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -91,7 +91,7 @@ * names for the TCO status bits. Size of the array is * returned as an output parameter. */ -const char * const *soc_tco_sts_array(size_t *a); +const char *const *soc_tco_sts_array(size_t *a);
/* * Resets the tco status registers. This function clears the tco_sts register @@ -186,14 +186,14 @@ * names for the SMI status register bits. Size of the array is * returned as an output parameter. */ -const char * const *soc_smi_sts_array(size_t *a); +const char *const *soc_smi_sts_array(size_t *a);
/* * This function returns array of string which represents * names for the STD GPE status register bits. * Size of the array is returned as an output parameter. */ -const char * const *soc_std_gpe_sts_array(size_t *a); +const char *const *soc_std_gpe_sts_array(size_t *a);
/* * This function gets the gpe0 dwX values from devicetree diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index 542997c..78903bb 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -24,7 +24,7 @@ #include <soc/pm.h>
static void print_num_status_bits(int num_bits, uint32_t status, - const char * const bit_names[]) + const char *const bit_names[]) { int i;
@@ -43,7 +43,7 @@
static uint32_t print_smi_status(uint32_t smi_sts) { - static const char * const smi_sts_bits[] = { + static const char *const smi_sts_bits[] = { [2] = "BIOS", [4] = "SLP_SMI", [5] = "APM", @@ -129,7 +129,7 @@
static uint16_t print_pm1_status(uint16_t pm1_sts) { - static const char * const pm1_sts_bits[] = { + static const char *const pm1_sts_bits[] = { [0] = "TMROF", [4] = "BM", [5] = "GBL", [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR", [15] = "WAK", @@ -155,7 +155,7 @@
static uint32_t print_tco_status(uint32_t tco_sts) { - static const char * const tco_sts_bits[] = { + static const char *const tco_sts_bits[] = { [0] = "NMI2SMI", [1] = "OS_TCO_SMI", [2] = "TCO_INIT", [3] = "TIMEOUT", [7] = "NEWCENTURY ", [8] = "BIOSWR ", @@ -214,7 +214,7 @@
static uint32_t print_gpe_sts(uint32_t gpe_sts) { - static const char * const gpe_sts_bits[] = { + static const char *const gpe_sts_bits[] = { [0] = "GPIO_0", [1] = "GPIO_1", [2] = "GPIO_2", [3] = "GPIO_3", [4] = "GPIO_4", [5] = "GPIO_5", diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c7c984c..a7268aa 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -44,7 +44,7 @@ UPD_DATA_REGION *UpdDataRgnPtr; VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase); UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); - memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); + memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); }
/* default to just enabling HDMI audio */ diff --git a/src/soc/intel/fsp_broadwell_de/pmutil.c b/src/soc/intel/fsp_broadwell_de/pmutil.c index bd19104..ccab1ce 100644 --- a/src/soc/intel/fsp_broadwell_de/pmutil.c +++ b/src/soc/intel/fsp_broadwell_de/pmutil.c @@ -29,7 +29,7 @@ #include <soc/pci_devs.h>
/* Print status bits with descriptive names */ -static void print_status_bits(u32 status, const char * const bit_names[]) +static void print_status_bits(u32 status, const char *const bit_names[]) { int i;
@@ -73,7 +73,7 @@ /* Print PM1 status bits */ static u16 print_pm1_status(u16 pm1_sts) { - static const char * const pm1_sts_bits[] = { + static const char *const pm1_sts_bits[] = { [0] = "TMROF", [4] = "BM", [5] = "GBL", @@ -117,7 +117,7 @@ /* Print SMI status bits */ static u32 print_smi_status(u32 smi_sts) { - static const char * const smi_sts_bits[] = { + static const char *const smi_sts_bits[] = { [2] = "BIOS", [3] = "LEGACY_USB", [4] = "SLP_SMI", diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 8fd6599..7d5bc3f 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -121,7 +121,7 @@ char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ int vt, txt, aes; msr_t microcode_ver; - static const char * const mode[] = {"NOT ", ""}; + static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown";
index = 0x80000000; diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index a23172e..632749d 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -34,7 +34,7 @@ }
/* HFSTS1[3:0] Current Working State Values */ -static const char * const me_cws_values[] = { +static const char *const me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", [ME_HFS_CWS_INIT] = "Initializing", [ME_HFS_CWS_REC] = "Recovery", @@ -54,7 +54,7 @@ };
/* HFSTS1[8:6] Current Operation State Values */ -static const char * const me_opstate_values[] = { +static const char *const me_opstate_values[] = { [ME_HFS_STATE_PREBOOT] = "Preboot", [ME_HFS_STATE_M0_UMA] = "M0 with UMA", [ME_HFS_STATE_M3] = "M3 without UMA", @@ -64,7 +64,7 @@ };
/* HFSTS1[19:16] Current Operation Mode Values */ -static const char * const me_opmode_values[] = { +static const char *const me_opmode_values[] = { [ME_HFS_MODE_NORMAL] = "Normal", [ME_HFS_MODE_DEBUG] = "Debug", [ME_HFS_MODE_DIS] = "Soft Temporary Disable", @@ -73,7 +73,7 @@ };
/* HFSTS1[15:12] Error Code Values */ -static const char * const me_error_values[] = { +static const char *const me_error_values[] = { [ME_HFS_ERROR_NONE] = "No Error", [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", [ME_HFS_ERROR_IMAGE] = "Image Failure", @@ -81,7 +81,7 @@ };
/* HFSTS2[31:28] ME Progress Code */ -static const char * const me_progress_values[] = { +static const char *const me_progress_values[] = { [ME_HFS2_PHASE_ROM] = "ROM Phase", [1] = "Unknown (1)", [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", @@ -94,7 +94,7 @@ };
/* HFSTS2[27:24] Power Management Event */ -static const char * const me_pmevent_values[] = { +static const char *const me_pmevent_values[] = { [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = @@ -131,13 +131,13 @@ };
/* Progress Code 0 states */ -static const char * const me_progress_rom_values[] = { +static const char *const me_progress_rom_values[] = { [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" };
/* Progress Code 1 states */ -static const char * const me_progress_bup_values[] = { +static const char *const me_progress_bup_values[] = { [ME_HFS2_STATE_BUP_INIT] = "Initialization starts", [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index aed8b99..a9061f8 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -512,14 +512,14 @@ u32 vmode; };
-unsigned long READL(void * p); -void WRITEL(unsigned long value, void * p); +unsigned long READL(void *p); +void WRITEL(unsigned long value, void *p);
#ifndef __PRE_RAM__ void display_startup(struct device *dev); #endif -void dp_init(void * _config); -void dp_enable(void * _dp); +void dp_init(void *_config); +void dp_enable(void *_dp); unsigned int fb_base_mb(void);
#endif /* __SOC_NVIDIA_TEGRA_DC_H */ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index e96a80c..9173e62 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -483,7 +483,7 @@
void clock_cpu0_config(void *entry) { - void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; + void *const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100;
write32(&maincpu_stack_pointer, (uintptr_t)_estack); write32(&maincpu_entry_point, (uintptr_t)entry); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index e66cbbd..febb420 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -38,7 +38,7 @@ struct tegra_dc dc_data;
int dump = 0; -unsigned long READL(void * p) +unsigned long READL(void *p) { unsigned long value;
@@ -55,7 +55,7 @@ return value; }
-void WRITEL(unsigned long value, void * p) +void WRITEL(unsigned long value, void *p) { if (dump) printk(BIOS_SPEW, "writel %p %08lx\n", p, value); diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 8a316f2..a9b8d7d 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -328,7 +328,7 @@ }
static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd, - u8 * data_ptr) + u8 *data_ptr) { u32 size = 1; u32 status = 0; @@ -1356,7 +1356,7 @@ printk(BIOS_SPEW, "%s: configuration updated by EDID.\n", __func__); }
-void dp_init(void * _config) +void dp_init(void *_config) { struct soc_nvidia_tegra124_config *config = (void *)_config; struct tegra_dc *dc = config->dc_data; @@ -1406,7 +1406,7 @@ return -1; }
-void dp_enable(void * _dp) +void dp_enable(void *_dp) { struct tegra_dc_dp_data *dp = _dp; struct tegra_dc *dc = dp->dc; diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 28d1603..d08e26f 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -290,7 +290,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, u32 same_freq); -void clock_cpu0_config(void * entry); +void clock_cpu0_config(void *entry); void clock_cpu0_remove_reset(void); void clock_halt_avp(void); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 51cfc8b..6ce2ba1 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -654,7 +654,7 @@ write32(rst_dev_clr_reg, val); }
-static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(clk_enb_l_set), CLK_RST_REG(clk_enb_h_set), CLK_RST_REG(clk_enb_u_set), @@ -664,7 +664,7 @@ CLK_RST_REG(clk_enb_y_set), };
-static u32 * const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(clk_enb_l_clr), CLK_RST_REG(clk_enb_h_clr), CLK_RST_REG(clk_enb_u_clr), @@ -674,7 +674,7 @@ CLK_RST_REG(clk_enb_y_clr), };
-static u32 * const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(rst_dev_l_set), CLK_RST_REG(rst_dev_h_set), CLK_RST_REG(rst_dev_u_set), @@ -684,7 +684,7 @@ CLK_RST_REG(rst_dev_y_set), };
-static u32 * const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(rst_dev_l_clr), CLK_RST_REG(rst_dev_h_clr), CLK_RST_REG(rst_dev_u_clr), @@ -694,7 +694,7 @@ CLK_RST_REG(rst_dev_y_clr), };
-static void clock_write_regs(u32 * const regs[DEV_CONFIG_BLOCKS], +static void clock_write_regs(u32 *const regs[DEV_CONFIG_BLOCKS], u32 bits[DEV_CONFIG_BLOCKS]) { int i = 0; diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index b54614f..b892c60 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -23,7 +23,7 @@ #include <soc/display.h>
int dump = 0; -unsigned long READL(void * p) +unsigned long READL(void *p) { unsigned long value;
@@ -40,7 +40,7 @@ return value; }
-void WRITEL(unsigned long value, void * p) +void WRITEL(unsigned long value, void *p) { if (dump) printk(BIOS_SPEW, "writel %p %08lx\n", p, value); diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 5a9d5a5..532ffc3 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -569,7 +569,7 @@ return tegra_mipi_calibrate(dsi->mipi); }
-static const char * const error_report[16] = { +static const char *const error_report[16] = { "SoT Error", "SoT Sync Error", "EoT Sync Error", diff --git a/src/soc/nvidia/tegra210/flow_ctrl.c b/src/soc/nvidia/tegra210/flow_ctrl.c index ea5b279..0eb8357 100644 --- a/src/soc/nvidia/tegra210/flow_ctrl.c +++ b/src/soc/nvidia/tegra210/flow_ctrl.c @@ -36,7 +36,7 @@ #define FLOW_CTRL_CPU1_CSR 0x18 #define FLOW_CTRL_CC4_CORE0_CTRL 0x6c
-static void *tegra_flowctrl_base = (void*)TEGRA_FLOW_BASE; +static void *tegra_flowctrl_base = (void *)TEGRA_FLOW_BASE;
static const uint8_t flowctrl_offset_halt_cpu[] = { FLOW_CTRL_HALT_CPU0_EVENTS, diff --git a/src/soc/nvidia/tegra210/include/soc/id.h b/src/soc/nvidia/tegra210/include/soc/id.h index 0903ba9..42b2be6 100644 --- a/src/soc/nvidia/tegra210/include/soc/id.h +++ b/src/soc/nvidia/tegra210/include/soc/id.h @@ -23,7 +23,7 @@ static inline int context_avp(void) { const uint32_t avp_id = 0xaaaaaaaa; - void * const uptag = (void *)(uintptr_t)TEGRA_PG_UP_BASE; + void *const uptag = (void *)(uintptr_t)TEGRA_PG_UP_BASE;
return read32(uptag) == avp_id; } diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c index f71e5e8..97eb3de 100644 --- a/src/soc/nvidia/tegra210/mtc.c +++ b/src/soc/nvidia/tegra210/mtc.c @@ -31,7 +31,7 @@ struct region_device fh; struct cbfsf mtc_file;
- void * const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS; + void *const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS; void *dvfs_table; size_t (*mtc_fw)(void **dvfs_table) = (void *)mtc;
diff --git a/src/soc/nvidia/tegra210/power.c b/src/soc/nvidia/tegra210/power.c index 6b22f5a..cef5b99 100644 --- a/src/soc/nvidia/tegra210/power.c +++ b/src/soc/nvidia/tegra210/power.c @@ -36,7 +36,7 @@ return POWER_GATE; }
-static const char * const power_gate_string[] = { +static const char *const power_gate_string[] = { [POWER_GATE] = "Gat", [POWER_UNGATE] = "Ungat", }; diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index f8f4e4d..3a5b80b 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -24,7 +24,7 @@ #define CRPORT_RX_OVRD_IN_HI 0x1006 #define CRPORT_TX_ALT_BLOCK 0x102d
-static u32 * const tcsr_usb_sel = (void *)0x1a4000b0; +static u32 *const tcsr_usb_sel = (void *)0x1a4000b0;
struct usb_qc_phy { u32 ipcat; diff --git a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h index 184540c..0833934 100644 --- a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h +++ b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h @@ -17,14 +17,14 @@ #define CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H
/* These are pointers to function pointers. Double indirection! */ -static void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030; -static void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044; -static void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048; -static void * * const irom_spi_sf_read_ptr = (void * *)0x02020058; -static void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070; +static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030; +static void **const irom_msh_read_from_fifo_emmc_ptr = (void **)0x02020044; +static void **const irom_msh_end_boot_op_emmc_ptr = (void **)0x02020048; +static void **const irom_spi_sf_read_ptr = (void **)0x02020058; +static void **const irom_load_image_from_usb_ptr = (void **)0x02020070;
#define SECONDARY_BASE_BOOT_USB 0xfeed0002 -static u32 * const iram_secondary_base = (u32 *)0x02020018; +static u32 *const iram_secondary_base = (u32 *)0x02020018;
/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */ #define OM_STAT_SDMMC 0x4 diff --git a/src/soc/samsung/exynos5250/include/soc/power.h b/src/soc/samsung/exynos5250/include/soc/power.h index dbcc4fe..b5a4c33 100644 --- a/src/soc/samsung/exynos5250/include/soc/power.h +++ b/src/soc/samsung/exynos5250/include/soc/power.h @@ -63,7 +63,7 @@ } __packed; check_member(exynos5_power, ps_hold_ctrl, 0x330c);
-static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE; +static struct exynos5_power *const exynos_power = (void *)EXYNOS5_POWER_BASE;
/** * Perform a software reset. diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index e955dcd..1fae4d7 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -916,7 +916,7 @@ void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val, unsigned char lanecnt) { - void * reg_list[DP_LANE_CNT_4] = { + void *reg_list[DP_LANE_CNT_4] = { &dp_regs->ln0_link_training_ctl, &dp_regs->ln1_link_training_ctl, &dp_regs->ln2_link_training_ctl, diff --git a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h index 4bda93c..40af40b 100644 --- a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h +++ b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h @@ -17,14 +17,14 @@ #define CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H
/* These are pointers to function pointers. Double indirection! */ -static void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030; -static void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044; -static void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048; -static void * * const irom_spi_sf_read_ptr = (void * *)0x02020058; -static void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070; +static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030; +static void **const irom_msh_read_from_fifo_emmc_ptr = (void **)0x02020044; +static void **const irom_msh_end_boot_op_emmc_ptr = (void **)0x02020048; +static void **const irom_spi_sf_read_ptr = (void **)0x02020058; +static void **const irom_load_image_from_usb_ptr = (void **)0x02020070;
#define SECONDARY_BASE_BOOT_USB 0xfeed0002 -static u32 * const iram_secondary_base = (u32 *)0x02020018; +static u32 *const iram_secondary_base = (u32 *)0x02020018;
/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */ #define OM_STAT_SDMMC 0x4 diff --git a/src/soc/samsung/exynos5420/include/soc/power.h b/src/soc/samsung/exynos5420/include/soc/power.h index 4fb96fd..c5709a5 100644 --- a/src/soc/samsung/exynos5420/include/soc/power.h +++ b/src/soc/samsung/exynos5420/include/soc/power.h @@ -76,7 +76,7 @@ } __packed; check_member(exynos5_power, ps_hold_ctrl, 0x330c);
-static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE; +static struct exynos5_power *const exynos_power = (void *)EXYNOS5_POWER_BASE;
/** * Perform a software reset. diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 7086da8..4a5c105 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -45,12 +45,12 @@ #define CORE_STATE_SWITCH_CLUSTER (1 << 4)
/* The default address to re-power on a code. */ -#define CORE_RESET_INIT_ADDRESS ((void*)0x00000000) +#define CORE_RESET_INIT_ADDRESS ((void *)0x00000000)
/* Vectors in BL1 (0x02020000 = base of iRAM). */ -#define VECTOR_CORE_SEV_HANDLER ((void*)(intptr_t)0x02020004) -#define VECTOR_LOW_POWER_FLAG ((void*)(intptr_t)0x02020028) -#define VECTOR_LOW_POWER_ADDRESS ((void*)(intptr_t)0x0202002C) +#define VECTOR_CORE_SEV_HANDLER ((void *)(intptr_t)0x02020004) +#define VECTOR_LOW_POWER_FLAG ((void *)(intptr_t)0x02020028) +#define VECTOR_LOW_POWER_ADDRESS ((void *)(intptr_t)0x0202002C)
/* The data structure for the "CPU state" memory page (shared with kernel) * controlling cores in active cluster. Kernel will put starting address for one @@ -93,12 +93,12 @@ }
/* Waits the referenced address to be ready (non-zero) and then jump into it. */ -static void wait_and_jump(volatile uint32_t* reference) +static void wait_and_jump(volatile uint32_t *reference) { while (!*reference) { wfe(); } - jump_bx((void*)*reference); + jump_bx((void *)*reference); }
/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ @@ -127,7 +127,7 @@
/* Initializes the CPU states to reset state. */ static void init_exynos_cpu_states(void) { - memset((void*)exynos_cpu_states, 0, sizeof(*exynos_cpu_states)); + memset((void *)exynos_cpu_states, 0, sizeof(*exynos_cpu_states)); exynos_cpu_states->cpu_states[0] = CORE_STATE_RESET; exynos_cpu_states->cpu_states[1] = CORE_STATE_SECONDARY_RESET; exynos_cpu_states->cpu_states[2] = CORE_STATE_SECONDARY_RESET; @@ -176,7 +176,7 @@ /* Standard Exynos suspend/resume. */ if (exynos_power->inform1) { exynos_power->inform1 = 0; - jump_bx((void*)exynos_power->inform0); + jump_bx((void *)exynos_power->inform0); /* never returns. */ }
-
Elyes HAOUAS (Code Review)