Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48264 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters
change TCC offset to 10C.
BUG=b:174547185 TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang sheng-liang.pan@quanta.corp-partner.google.com Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48264/1
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 9c4aa47..c60528c 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" - register "tcc_offset" = "5" # TCC of 95 + register "tcc_offset" = "10" # TCC of 90
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 18,
Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48264 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
Patch Set 1: Code-Review+1
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48264 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48264/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/voxel/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/48264/1/src/mainboard/google/voltee... PS1, Line 4: register "tcc_offset" = "10" # TCC of 90 You can remove it. It is the same setting as baseboard. https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...
Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Sumeet R Pawnikar, YH Lin, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48264
to look at the new patch set (#2).
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters
remove TCC offset setting in overridetree.cb, use defualt setting in baseboard.
BUG=b:174547185 TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang sheng-liang.pan@quanta.corp-partner.google.com Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48264/2
Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Sumeet R Pawnikar, YH Lin, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48264
to look at the new patch set (#3).
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters
remove TCC offset setting in overridetree.cb, use default setting(# TCC of 90) in baseboard.
BUG=b:174547185 TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang sheng-liang.pan@quanta.corp-partner.google.com Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48264/3
Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48264 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48264/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/voxel/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/48264/1/src/mainboard/google/voltee... PS1, Line 4: register "tcc_offset" = "10" # TCC of 90
You can remove it. It is the same setting as baseboard. […]
done
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48264 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
Patch Set 3: Code-Review+1
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48264 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48264/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48264/3//COMMIT_MSG@14 PS3, Line 14: Add BRANCH=volteer
Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Sumeet R Pawnikar, YH Lin, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48264
to look at the new patch set (#4).
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters
remove TCC offset setting in overridetree.cb, use default setting(# TCC of 90) in baseboard.
BUG=b:174547185 BRANCH=volteer TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang sheng-liang.pan@quanta.corp-partner.google.com Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48264/4
Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48264 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48264/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48264/3//COMMIT_MSG@14 PS3, Line 14:
Add BRANCH=volteer
done
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48264 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
Patch Set 4: Code-Review+2
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48264 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters
remove TCC offset setting in overridetree.cb, use default setting(# TCC of 90) in baseboard.
BUG=b:174547185 BRANCH=volteer TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang sheng-liang.pan@quanta.corp-partner.google.com Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48264 Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-by: David Wu david_wu@quanta.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved David Wu: Looks good to me, but someone else must approve Sheng-Liang Pan: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 9c4aa47..2dd1566 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" - register "tcc_offset" = "5" # TCC of 95
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 18,
-
David Wu (Code Review) -
Sheng-Liang Pan (Code Review)
-
Sumeet R Pawnikar (Code Review)
-
Tim Wawrzynczak (Code Review)